How to drive the LED in ADPD4101 sensor?

Hi  Sudharsan,

Have you verified if your register read & write are working?

With regard to the LED drivers, can you let us know your schematic of the LED(s) and/or PD(s)? The LED drivers of ADPD4101 are current sink and the LED(s) should be supplied with VLED. 

Regards,

Glen B. 

Hi Glen,

Thanks for your reply.

I2C read/write is working fine. LEDs are 1A, 2A, 3A, 4A and 4B

I have resolved it, as I was not turning on the 1MHz LF OSC

Its working. I am moving forward to do PPG measurement.

I'll give you an update on PPG stuffs. I need your support on this sensor's software development, as I am new to this.

Thanks and Regards

Sudharsan

Thanks Sudharsan! Let us know if you need assistance.

Regards,

Glen B.

Hi Glen,

I need your support on PPG measurements and I hope you know that I am using ADPD4101 sensor

I have configured following registers

1. Standby mode during write operations, Go mode after write operation

2. 1 MHz LF Oscillator

3. FIFO interrupt configured and Watermark level set to 20 bytes and GPIO 0 pin configured as an interrupt

4. LEDs 1A, 2A, 3A, 4A, 4B configured with appropriate current settings - Able to operate

5. Sampling frequency - 300 Hz

6. Timeslot A has been selected - I request you to give me more information about Timeslots

a) How many Timeslots can be used ? Currently I have used only Timeslot A. Is there anything like, we have to use only Timeslot A and  B for LEDs. C and D for Inputs/ GPIOs. Please clarify the same. I have also attached My HRM sensor schematic

7. LED pulse width and offset 20us and 16us respectively

8. In Register 0x0100 written value = 0x4000       Enable Channel 2   //<! impulse mode with offset = 0

9. In Register 0x0101 written value = 0x00E6      Skip preconditioning, Band pass filter bypassed

10. In Register 0x0110 written value = 0x0003     Configure number of bytes - 3 bytes (Max 4 bytes)

11. TIA gain 100k and Vref = 0.88v

12. In Register 0x0107 written value = 0x010C    No. of ADC pulses 

13. In Register 0x0108 written value = 0x1000     float mode, minimum period

14. In Register 0x010A written value = 0x0203     Integrator pulse width, bandpass filter powered down

15. In Register 0x010B written value = 0x01A0    Integrator pulse timing offset

16. In Register 0x010C written value = 0x0210    Modulation pulse width and offset

17. In Register 0x010C written value = 0x0210    IN2 connected to VC1...IN4, IN8 connected to VC2

b) I need to read the Channel 1 and Channel 2. How do I specifically read from channel 1 and Channel 2 ??

c) Currently I am getting 3 bytes from FIFO on every single read. How do I verify whether I am receiving correct PPG outputs.

I thought that I would get 20 bytes after periodic read from FIFO. But I have got 3 bytes every time. What is that DATA FORMAT bytes actually that I configured with ?

d)  Decimation factor - I did not set this register. What do I need to set with ? or Does this very essential to set? (This is to calculate ODR right ??)

e) Does it have standard sampling mode and Digital Integration mode ? If so, need to know detailed information.

f) What is the Dark signal registers for?  and  What is the Lit signal registers for?

Regards

Sudharsan

Hi Sudharsan,

You can find the answers to most of your questions in the ADPD4100/ADPD4101 datasheet. You can start with simple configuration such as those come with our evaluation software Applications Wavetool.

For your convenience, please refer to my comments below:

6. Timeslot A has been selected - I request you to give me more information about Timeslots

a) How many Timeslots can be used ? Currently I have used only Timeslot A. Is there anything like, we have to use only Timeslot A and  B for LEDs. C and D for Inputs/ GPIOs. Please clarify the same. I have also attached My HRM sensor schematic

The ADPD4101 supports up to 12 timeslots. There is no specific application associated with any timeslot. You can use a timeslot for any measurement. The input pins can be configured different in each timeslot. The GPIOs can be configured quite differently. Please refer to register map for registers 0x0023 and 0x0024 for details.

b) I need to read the Channel 1 and Channel 2. How do I specifically read from channel 1 and Channel 2 ??

You can enable CH2 by setting bit[14] of register 0x0100 for timeslot A, register 0x0120 for timeslot B, and so on. The data in the FIFO is organized sequentially as timeslot A, timeslot B, ... For instance, if you have timeslots A with CH1, timeslot B with CH1 & CH2, and timeslot C with CH1, then the data stream as following: [A_CH1]-[B_CH1]-[B_CH2]-[C_CH1]-[A_CH1]]-[B_CH1]-[B_CH2]-[C_CH1]- ..., depending on your FIFO threshold setting in register 0x0006.

c) Currently I am getting 3 bytes from FIFO on every single read. How do I verify whether I am receiving correct PPG outputs. 

I thought that I would get 20 bytes after periodic read from FIFO. But I have got 3 bytes every time. What is that DATA FORMAT bytes actually that I configured with ?

I am not sure how your code reads the FIFO. Please check if it reads all the data in the FIFO for each FIFO interrupt handling.

d) Decimation factor - I did not set this register. What do I need to set with ? or Does this very essential to set? (This is to calculate ODR right ??)

The decimation factor is for reducing the ODR. Check the register map of register 0x0112/0x0132/0x0152... for details.

e) Does it have standard sampling mode and Digital Integration mode ? If so, need to know detailed information.

The ADPD4101 supports multiple acquisition mode, including float mode, continuous mode, digital integration mode, and other modes. Refer to the datasheet for details.

f) What is the Dark signal registers for?  and  What is the Lit signal registers for?

In measurement with photodiode (PD), there is very small dark current with no photons hitting the PD if the PD is reverse biased (that is very typical for PD to achieve fast response). The dark current is acquired as dark signal and saved in the dark signal register. The LIT is the sample when there are photons hitting the PD. Lit minus Dark will give the true photocurrent. Please refer to Figure 23 in the datasheet for details.

Regards,

Glen B.

Hi Glen,

Thanks for your reply.

Have a query on FIFO TH and Read data.

FIFO data reading from ADPD410X_REG_FIFO_DATA - 0x002F register

I have added snippet. Please verify it

/*******************Setting up ADPD410x************************/
{ 
        data = 0x4000;                       //Enable Channel 2, Standard sampling mode, Rin 500 ohms
	    ret = adpd410x_reg_write(p_instance, ADPD410X_REG_TS_CTRL(m_timeslot_no), data);       //0x0100

        data = 0x1410;                       //LED Pulse width set to 20us & offset 16us
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_LED_PULSE(m_timeslot_no), data); //0x0109

        data = 0x00E6;                       //Skip preconditioning, Band pass filter bypassed < precond = 0 >
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_TS_PATH(m_timeslot_no), data); //0x0101

        data = 0x0004;                       //Configure number of bytes - 4 bytes (Max 4 bytes)
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_DATA1(m_timeslot_no), data); //0x0110

        data = 0x02C1;                       //TIA gain 100k, Vref = 0.88V
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_AFE_TRIM(m_timeslot_no), data); //0x0101

        data = 0x010C;                       //[15:8] = No of pulses...[7:0] Number of seq repeats //Eg: 1 pulse * 5 repeat = 12 pulses
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_COUNTS(m_timeslot_no), data); //0x0107

        data = 0x0000;                       //continuous connect mode
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_PERIOD(m_timeslot_no), data); //0x0108

        data = 0x0203;                       //Integrator pulse width - 3us, bandpass filter powered down
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_INTEG_WIDTH(m_timeslot_no), data); //0x010A

        data = 0x0210;                       //Integrator pulse timing offset 
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_INTEG_OFFSET(m_timeslot_no), data); //0x010B

        data = 0x0001;                       //No Modulation //0:7 cannot be 0
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_MOD_PULSE(m_timeslot_no), data); //0x010C


        data = 0x0099;                       // -++- int pattern
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_ADC_OFF1(m_timeslot_no), data); //0x010D
        if(ret != NRF_SUCCESS)
            return ret;

        data = 0x0000;                       //No offset - review if needed
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_ADC_OFF1(m_timeslot_no), data); //0x010E
        if(ret != NRF_SUCCESS)
            return ret;

        data = 0x0000;                       //No offset - review if needed
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_ADC_OFF2(m_timeslot_no), data); //0x010F

        data = 0x0000;                       //No decimation
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_DECIMATE(m_timeslot_no), data); //0x0112
        
        data = 0x0000;                       //All inputs single Ended, VC1, VC2 set to AVDD during sleep
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_INPUT_CFG, data); 
              
        data = 0x4000;                       //IN8 connected to VC2
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_INPUTS(m_timeslot_no), data);  //0x0102 

        data = 0x9000;                       //IN8 connected to VC2 during sleep
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_INPUT_SLEEP, data); //0x0020
}

{
/***********GPIO configs*******************/
        reg_data = 0x0002;          //gpio0 is output, normal
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_GPIO_CFG, reg_data);

        reg_data = 0x0002;          //gpio0 interruput x (pin cgf0 configured as output)
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_GPIO01, reg_data);

/*************FIFO configs*****************/
        reg_data = 0x000A;          //20 bytes FIFO
        ret = adpd410x_reg_write(p_instance, ADPD410X_REG_FIFO_TH, reg_data);

        ret = adpd410x_reg_read(p_instance, ADPD410X_REG_INT_ENABLE_XD, &reg_data);
        if(ret == SUCCESS)
        {
            reg_data = (reg_data & 0x7FFFU) | ((0x1U) << 15U);
            ret = adpd410x_reg_write(p_instance, ADPD410X_REG_INT_ENABLE_XD, reg_data);  /* Enable INTX */
        }

        if(ret == SUCCESS)
        {
            ret = adpd410x_reg_read(p_instance, ADPD410X_REG_INT_ENABLE_YD, &reg_data);
            if(ret == SUCCESS)
            {
              /* Overflow and Underflow enabled */
              reg_data = (reg_data & 0x9FFFU) | ((0x1U) << 14U) | ((0x1U) << 13U);
              
              /* write register with prepared value on INT Y */
              ret = adpd410x_reg_write(p_instance, ADPD410X_REG_INT_ENABLE_YD, reg_data);  /* Enable INTY */
            }
        }
}


/****************Read FIFO byte count and FIFO data********************/

{
	int32_t ret;                           //0x0000
	ret = adpd410x_reg_read(p_instance, ADPD410X_REG_FIFO_STATUS, &bytes);

    print("Data count = %X", bytes);
	bytes &= BITM_INT_STATUS_FIFO_FIFO_BYTE_COUNT;
	return bytes;
}

{
    int32_t ret;
    uint8_t cnt = 0;
    uint16_t data_buff[20] = {0};
    uint16_t bytes;

    adpd410x_get_FIFO_bytecount(p_instance, bytes);

	for(cnt = 0; cnt < bytes; cnt++){          //0x002F
            adpd410x_reg_read(p_instance, ADPD410X_REG_FIFO_DATA, (data_buff + cnt));
            print("Data = %02X", *(data_buff + cnt));
	}
}

I have configured only IN8 connected to channel VC2 (Please refer the schematic which I attached previously).

In DATA_FORMAT register configured, Number of bytes of signal data to be written to the FIFO = 4 bytes

I am able to read FIFO data. When I read FIFO I have got byte count as 8 (Reading periodically in every 5 seconds once)

Please refer the screenshot below

I am unable to get the FIFO data repeatedly and also FIFO TH level not reached if I set with 10, 20, etc.

I have written code to read the FIFO data, Is that Right? Please check the register configs also

Looking ahead for your comments

Regards

Sudharsan

Hi Glen,

I have observed the following registers

FIFO byte count  (0x0000) which was continuously incrementing. In my program 

FIFO INT status data (0x0001) - When I read this register its was showing value as 0x8001 when it reaches FIFO Threshold of 100 bytes that I defined.

Using GPIO0 as an interrupt pin which I configured as an Output normal.

Register - 0x0022   value - 0x0002

Register - 0x0023   value - 0x0002

Is this config right?

But only thing is that, I am not getting any interrupt on controller side even after status showing correct values. Looking ahead for your comments

Regards

Sudharsan

HI Sudharsan,

I will ask one of our software engineer to check your code.

Regards,

Glen B.

Hi Sudharsan,

In Host how do configured the IRQ setting? is it falling edge or rising edge?

And in your code i saw the threshold level settings, you have to change the code like below.

reg_data = 0x000A; //20 bytes FIFO
ret = adpd410x_reg_write(p_instance, ADPD410X_REG_FIFO_TH, (reg_data - 0x01U);

Regards,

Sathishkumar K

Hi Sathish,

Its falling edge configuration on controller side.

FIFO TH - 0x000A was for our testing.

I am currently setting with ( 256 - 1 = 255 (0xFF)) 0xFF bytes as FIFO Threshold. Usually we will call it as FIFO Watermarking right?....and when FIFO buffer filling reaches the Watermark level, it will trigger the interrupt on configured pin right? 

I hope the other register settings that I did correctly.

Regards

Sudharsan

Hi Sudharsan,

Yes, it's watermark level for FIFO. whenever the FIFO reached the watermark level it will trigger the interrupt.

You need to configure register 0x22 as inverted output (0x0003U). Since your host expecting falling edge to trigger interrupt.

Change the register value and check.

Regards,

Sathishkumar K

Hi Sathish,

I am getting interrupt on both settings in 0x22 register (output inverted and output normal)

I have configured as a output inverted and tested and also I have tested with output normal.

I am getting PPG values from FIFO but I still have no clarity on following register settings. Is this register settings are fine to move forward to calculate Raw PPG to HRM ???

Currently, we are preferring continuous connect mode. No modulation and No ADC offset has been selected. Please refer the below settings and suggest your comments

1. Selected continuous connect mode 

data = 0x0000, Reg = 0x0108 

2. Gain setting - TIA gain 100k, Vref = 0.88V  //LEDs current setting is 50mA

data = 0x02C1, Reg = 0x0104

3. Skipped the PRECON and Testing with signal data by passing through "TIA + BPF + INT + ADC" and  "TIA + INT + ADC"       

data = 0x00DA or 0x00E6, Reg =  0x0101

4. when data = 0x99 - getting negative values as well  //Chop settings

data = 0x00AA, Reg = 0x010D

5. ADC pulses = 32, Integrator Pulse width data = 3 us , Integrator Offset data = 0x0210 //16.5us

Regards

Sudharsan

Hi Sathish,

I am getting interrupt on both settings in 0x22 register (output inverted and output normal)

I have configured as a output inverted and tested and also I have tested with output normal.

I am getting PPG values from FIFO but I still have no clarity on following register settings. Is this register settings are fine to move forward to calculate Raw PPG to HRM ???

Currently, we are preferring continuous connect mode. No modulation and No ADC offset has been selected. Please refer the below settings and suggest your comments

1. Selected continuous connect mode 

data = 0x0000, Reg = 0x0108 

2. Gain setting - TIA gain 100k, Vref = 0.88V  //LEDs current setting is 50mA

data = 0x02C1, Reg = 0x0104

3. Skipped the PRECON and Testing with signal data by passing through "TIA + BPF + INT + ADC" and  "TIA + INT + ADC"       

data = 0x00DA or 0x00E6, Reg =  0x0101

4. when data = 0x99 - getting negative values as well  //Chop settings

data = 0x00AA, Reg = 0x010D

5. ADC pulses = 32, Integrator Pulse width data = 3 us , Integrator Offset data = 0x0210 //16.5us

Regards

Sudharsan

Hi Sudharsan,

Please follow the example below to config your sensor for PPG measurement:

################################################################
## ADPD4100 Reference Config File, single-ended IN1 only, timeslot A only
## Please review config file for your design. This is a generic config file.
0009 0080 # 32MHz trim - trim your own clock
000B 02B2 # 1MHz trim - trim your own clock
000C 0012 # 32kHz trim - trim your own clock
000D 2710 # 100 Hz
000F 0006 # enable 1MHz osc
0020 0004 # in1 connected to vc1 during sleep, everything else floating
0021 0000 # all inputs single ended, vc1 set to Vdd during sleep
0022 0003 # gpio0 is output, inverted
0023 0002 # intx to gpio0
0014 8000 # fifo thresh interrupt to intx
0006 00FF # fifo threshold 128 bytes

## timeslot A - continuous connect mode

0100 0000 # Rin = 500, tsA offset = 0, skip subsample
0101 40DA # path = TIA + BPF + INT + ADC
0102 0001 # IN1 to channel 1, others disconnected
0103 5002 # precondition inputs to TIA_Vref, VC1 active state = V_delta
0104 03C0 # Rf = 200k Rint = 400k
0105 0017 # 38 mA on LED1A
0106 0000
0107 0104 # 4 pulses
0108 0000 # period set by automatic period of continuous connect mode
0109 0210 # led width= 2us led offset=16 us
010A 0003 # integrator width=3 us
010B 0210 # integrator offset=16.5 us - ADJUST FINE OFFSET
010C 0001 # no modulation
0110 0003 # signal size = 3 bytes
010D 0099 # -++- int pattern
010E 0000 # NO OFFSET - review if needed
010F 0000 # NO OFFSET - review if needed
0112 0000 # no decimation

You need to make some adjustment to the registers below:

Adjust register 0x0104: work with register 0x0105 and/or 0x0106 and adjust the TIA gain accordingly to avoid TIA saturation, recommended output at 70% full scale (8192 LSB per pulse as full scale. For instance, for 4-pulse config with chopping by register 0x010D, 70% full scale is 8192x4x0.7 = 23,000 LSBs)

Adjust register 0x0105/0x0106 for LED current: please note at anytime only one group of LED drivers can be used, either LED1A/2A/3A/4A or LED1B/2B/3B/4B, not both.

Adjust register 0x0104: increase the pulse number to multiples of 4 to improve SNR

Adjust register 0x010B: change the integrator offset with a reflector setup to optimize the zero-crossing. Please note the zero-crossing changes with the TIA gain so the optimal integrator offset needs to be optimized for each TIA gain.

Hope the information above helps.

Regards,

Glen B.

Thank you Glen

Hi,

I would request you to verify the PPG logs with respect to the register settings.

Please find the attached sheet which is having the sample PPG waveforms and entire register settings.

7536.PPG_logs.xlsx

Looking forward for your comments

Thanks

Sudharsan

Hi Sudharsan,

The data in your spreadsheet doesn't look like PPG signal. Before we debug other issue, can you add the register 0x00B0 with 0x0010 to your config file and check if you get output 0x020100 (decimal 131328)? If you get a different number, there is something wrong with your FIFO reading. 

Regards,

Glen B.

Hi Glen,

I did not understand that you mentioned the register address 0x00B0. 

Are you really pointing to 0x00B0 register ?? If Yes, there is no register address 0x00B0 mentioned in ADPD4101 datasheet.

I request you to check my register configurations that I have attached in that spread-sheet itself. I have copied the register settings which you have posted. 

Please refer this below post...My register settings are exactly matching with that

ez.analog.com/.../394040

Regards

Sudharsan

Hi Glen,

Please check the Raw PPG data and the overall our register settings.

I request you to review the below spread sheet

3377.RawPPG_vs_FilteredData_28June.xlsx

Regards,

Sudharsan

Hi Glen,

These all the below register setting which I have specifically changed.

Reg:       Data:

 0x0100   0x4000  //Enabled channel-2

 0x0107   0x0104  //ADC pulse = 4
 0x0109   0xFF0A  //LED pulse-width and offset
 0x010D   0x0099  //Register pattern -++-

Please check the Raw PPG data which I have collected and Please don't forget to reply for the below also

" I did not understand that you mentioned the register address 0x00B0. 

Are you really pointing to 0x00B0 register ?? If Yes, there is no register address 0x00B0 mentioned in ADPD4101 datasheet "

Regards,

Sudharsan

Hi Sudharsan,

You data doesn't look like PPG signal. There are a few strange settings in your config, including

-  [0100]4000   # it looked like you enabled both CH1 and CH2; however, your register [0102]4000 indicates that only IN8 connecting to CH2. When you have CH2 enabled,  both CH1 and CH2 data are written to FIFO with size defined by resigter [0110]0003.

-  [0109]FF0A  # indicate LED pulse width of 255us with 10us offset. What exactly do you plan to achieve? The typical LED pulse is 2us or 3us.

-  [0104]03C0 and [0106]0036 # What is the distance between your LED and PD? With TIA gain of 200k and LED3A current of 0x36 (or 81mA), the TIA may be saturated already.

With regard to register 0x00B0, it is not published in the datasheet. We suggest customers this register when we suspect there is an issue with the I2C or SPI FIFO reading.

I strongly recommend that you contact your local ADI application engineer for a meeting with us so that we can review your design and solve your problem more efficiently. 

Regards,

Glen B.

Thank you Glen

We were setting the LED pulse high as our application is Finger probing application and not wrist worn application. We are trying to get the PPG data and not getting it yet.

Please refer the image that I attached here

The distance between LED and Photo diode is 10-15mm and it is placed facing each other and not side by side.

However we have a contact with local representative.

Thanks

Sudharsan

Hi Sudharsan,

Thanks for the picture. 

I assume you tested with red or IR LED(s) for your transmissive PPG. Is it correct? As mentioned earlier, your setting of register 0x0109 is not correct. 

 Please ask you local representative to schedule a meeting with us if you like.

Regards,

Glen B.