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ADN8833 Capacitor and Inductor Selection

Thread Summary

The user inquired about the margin and numerical values for ΔV, Vsw_out, and Vin when using a 10 μF ceramic capacitor with the ADN8833, as recommended in the datasheet. The final answer stated that the worst-case ripple occurs at Vsw_out = 1/2 Vin, and if the ripple is larger than desired, capacitance can be increased while maintaining the recommended product of capacitance and inductance. The accompanying answer noted that Vsw_out at 1/2 Vin is approximately at minimum tec current.
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Please advise me again.

I read a ADN8833 datasheet. (Rev. A | Page 18 of 23)

Recommended capacitors is 10μF.

>A 10 μF ceramic capacitor rated at 10 V is the minimum recommended value.

>Increasing the capacitance reduces the switching ripple that couples into the power supply but increases the capacitor size.

I'm OK.

When 10 μF was chosen, how much numerical value was substituted for Δ V, Vsw_out, Vin?

I'd like to know about the margin of the fixed number for a better design.

Would it be considered by the fixed number about the capacitance-voltage dependence?

Do I have to choose a bigger capacitor?

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