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emrekk
Hi,   I am working on FMC DAQ2 board with Xilinx Zynq ZC706 Eval Board. And I am trying to implement reference HDL project with no-OS software project . I followed the steps below;   1. Build HDL project as described in the link below with "make -C projects/daq2/zc706". https://wiki.analog.com/resources/fpga/docs/build 2. After
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eee_33
Hi everyone,   I am recently  trying to understand how AD9361_iiostream.c code to work and I have some questions on the file AD9361_iiostream.c.  I understand that there is a limit to the buffer. Does this mean we can get maximum 1048576 samples in 1 millisecond with this created buffer?   "rxbuf =
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samba-guy
SigmaDSP is great for digital audio processing, but since the systems are becoming more digital from input to amplification, I'm actually missing PWM or Σ-Δ modulator outputs in order to directly drive an H-bridge for Class-D type amplification.   I've read that SigmaStudio processing clock is limited to its sample rate, so if I'd
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