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Hi, in this link   ==================================================================== / { fpga_axi: fpga-axi@0 { interrupt-parent = <&gic>; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x1>; ranges = <0 0 0 0 0xffffffff>; rx_dma: dma@80010000 { compatible = "adi,axi-dmac-1.00.a";

I have a customer using the FMCDAQ2 board. They want to change the sample rate to 800MSPS. They have removed the 125MHz oscillator and are applying a 100MHz signal to the AD9523. From the specs on PLL2 in the AD9523, I think that they have driven this PLL out of range on the low side, range is 3.6GHz to 4.0GHz. Is there any hook in the user
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hI   I  am using ADIS16485 IMU with using buffers and when i run this code i am getting junk data     #!/usr/bin/env python # Program to log and print the IMU data on screen # Author: Vishal Raveendranathan <> import iio import sys # To print the IIO library version print('IIO Library