I use the Analog Devices FMCMOTCON2 FPGA Mezzanine Card to prototype some industrial ethernet communications. On the PCB the serial management interfaces of the two Marvell PHYs are connected to the same MDC/MDIO bus. With our custom Ethernet MAC core, which works well with different PHYs (Marvell, Vitesse, Micrel) on our custom boards and several Xilinx evaluation boards, I was not able to access the management registers of the Marvell PHYs on the FMCMOTCON2. There always seems to be some kind of bus contention.
The PHYs on the FMCMOTCON2 are configured to have PHY address 0 and 1 using the default jumper settings. However according to IEEE 802.3 PHY address 0 is a broadcast address every PHY should listen and answer on.
I am wondering why there is a pull up resistor (1,5kOhm, R129) on the MDC line because as of IEEE 802.3 Std Section 2 (section 188.8.131.52 and 184.108.40.206) the pull up should be on the MDIO line instead. I compared the FMCMOTCON2 schematic to the FMCMOTCON1 schematic and there the pull-up is connected to MDIO indeed. Is this an error on the FMCMOTCON2 PCB? Is there any reason why the pull-up is on the MDC line?
The Marvell PHY does not interpret address 0 as broadcast, so it is safe to use this address.
The MDIO pullup is set from the FPGA for this design. You can get the HDL reference design from the Downloads section of this wiki page: Xilinx HDL Reference Design [Analog Devices Wiki]
This reference design shows how to use both PHYs.