AD2S1210 RDC Fault Reading and Clearing Questions

Hello I'm currently working on a driver using the parallel interface of the AD2S1210 and have two questions.

Question 1:

Is it required to write the fault register every time you leave configuration mode If you would like to read and clear the fault register on subsequent entries into the configuration mode. Currently my driver reads and clears the fault register as the last thing it does during initial configuration, and after this will only ever read the fault register, during normal driver usage.

My confusion comes from some of the wording in the data sheet. The data sheet states in the Clearing the Fault Register section on page 25:

"Note that the last valid register address written to the AD2S1210 prior to exiting configuration mode is again valid when reentering configuration mode. It is therefore recommended that when initial configuration of the AD2S1210 is complete, the fault address should be written to the AD2S1210 before leaving configuration mode. This simplifies the reading and clearing of the fault register in normal operation because it is now possible to access the position, velocity, and fault information by toggling the A0 and A1 pins without requiring additional register addressing. This implies that one only needs to toggle the A0 and A1 pins to a 1 and 1 state in order to read the fault information and that one does not need to write the fault address first, provided that it was written as part of an initial configuration."

However, also in the Clearing the Fault Register section in step 4 of the procedure required to clear the fault it states:

"The fault register should be read as described in the Reading from the AD2S1210 in Configuration Mode section."

Reading from the AD2S1210 in Configuration Mode section it states:

"The 8-bit address of the register to be read should then be written to the part, as described in the Writing to the AD2S1210 section."

This implies that to read valid fault data, you must write the fault address when in configuration mode, which in doing so will also clear the fault. This is supported in Figure 31 as it shows the fault address being written and data being received.

What I really want to know is does reading of the fault register without writing an address require that the last register written in configuration mode be the fault register even if this wasn't the last time the device was in configuration mode?

Question 2:

In order to clear the fault pins (LOT & DOS) does the nSAMPLE pin need to be transitioned a second time from high to low and held low for t_16?

Step 5 in clearing the fault register on page 25 indicates this transition of nSAMPLE needs to happen but doesn't specify a t_16, but Figure 31 shows the sample pin being held low a second time for t_16.

So is the delay of t_16 required second nSAMPLE transition.

Change formatting
[edited by: rcarney at 6:15 PM (GMT 0) on 21 Feb 2019]