ADuCM4050 Clock setting for 52MHz HCLK speed

Hi,

note: Must include flash and WDT drivers in operating higher than 26MHz.

you may refer to this sequence in order to generate 52MHz HCLK:

1. Route the clock signal to its corresponding pinout for verification of HCLK(debugging purposes).

2. Enable the clock source that you want to use >>adi_pwr_EnableClockSource()

     *you can skip this since the default clock source is HFOSC

3. Set the input clock source for PLL multiplexer >>adi_pwr_SetPLLClockMux()

4. Set the HP Buck load mode: The High load mode can be set when the system is running at greater than 26Mhz. >>adi_pwr_SetHPBuckLoadMode()

5. Program PLL frequency

        Configure PLL frequency to 52 MHz 
        MUL2 = 1
        N    = 26
        DIV2 = 1
        M    = 13
        Freq = HFOSC * (MUL2*N) / (DIV2*M) = 26 * (1 * 26) / (1*13) = 52

        use this api >>adi_pwr_SetPll()

6. Open Flash Controller Device >>adi_fee_Open()

7. Change flash wait state from 0 to 1: We need at least one wait state else the flash will not function correctly when running at 52 MHz (Necessary if system clock is greater than 26 MHz) >>adi_fee_ConfigureWaitStates()

8. Enable the clock source (this time with PLL) >>adi_pwr_EnableClockSource()

9. Set the PLL as source for the root clock multiplexer >>adi_pwr_SetRootClockMux()

10. Output HCLK to GPIO pin (port2, pin11) >>adi_pwr_SetGPIOClockOutput()

Regards,

BryanD

Hi,

note: Must include flash and WDT drivers in operating higher than 26MHz.

you may refer to this sequence in order to generate 52MHz HCLK:

1. Route the clock signal to its corresponding pinout for verification of HCLK(debugging purposes).

2. Enable the clock source that you want to use >>adi_pwr_EnableClockSource()

     *you can skip this since the default clock source is HFOSC

3. Set the input clock source for PLL multiplexer >>adi_pwr_SetPLLClockMux()

4. Set the HP Buck load mode: The High load mode can be set when the system is running at greater than 26Mhz. >>adi_pwr_SetHPBuckLoadMode()

5. Program PLL frequency

        Configure PLL frequency to 52 MHz 
        MUL2 = 1
        N    = 26
        DIV2 = 1
        M    = 13
        Freq = HFOSC * (MUL2*N) / (DIV2*M) = 26 * (1 * 26) / (1*13) = 52

        use this api >>adi_pwr_SetPll()

6. Open Flash Controller Device >>adi_fee_Open()

7. Change flash wait state from 0 to 1: We need at least one wait state else the flash will not function correctly when running at 52 MHz (Necessary if system clock is greater than 26 MHz) >>adi_fee_ConfigureWaitStates()

8. Enable the clock source (this time with PLL) >>adi_pwr_EnableClockSource()

9. Set the PLL as source for the root clock multiplexer >>adi_pwr_SetRootClockMux()

10. Output HCLK to GPIO pin (port2, pin11) >>adi_pwr_SetGPIOClockOutput()

Regards,

BryanD