Known Issues for ADuCM350 Silicon and Support Material

1. Placing valid data in the Slave Tx FIFO.
2. Set the BUS_CLR_EN bit in the I2CMCON register. If this bit is set, the master will initiate a Bus-Clear operation by sending up to 9 extra SCL cycles.
3. Set EARLYTXR bit in the I2CSCON register. Setting this bit enables a transmit request just after the positive edge on the SCL line during the read bit transmission.
4. Resetting the slave interface by disabling/enabling the slave.

In an attempt to minimize the power consumption of the I2C interface, it may be desirable to set the PCLK frequency to 1MHz and set the SCL frequency to 100kHz. Using the provided formula, this would lead to the following HIGH and LOW values in the I2CDIV register:

HIGH = (REQD_HIGH_TIME / PCLK_PERIOD) – 2

HIGH = ((10us / 2) / 1us) – 2

HIGH = 3

LOW = (REQD_LOW_TIME / PCLK_PERIOD) – 1

LOW = ((10us / 2) / 1us) – 1

LOW = 4

When these values are programmed, the I2C master will not function.

1. Use the adi_I2C_SetMasterClock() function to set the SCL frequency. Ensure to check for a valid return code.
2. Do not program values to the HIGH and LOW fields in the I2CDIV register which give a sum of less than 18 (0x12).

Clock stretching is an I2C feature that allows a slave device to temporarily pause communication by holding SCL low (for example, a slave device receives a READ request from a Master but, its Transmit FIFO is empty).

Clock stretching is enabled setting the STRETCHSCL bit in the I2CSCON register to 1. If this is done on the rising edge of SCL a glitch can occur. Other devices might interpret this as a real clock pulse and it could cause the bus to hang.