Question 1

ADuCM350 SDK v2.4.0.0 Released!

Accepted Answer

ADuCM350 SDK v2.4.0.0 Released! by ADIApproved 
 A new version of the ADuCM350 Software Development Kit (SDK) has been released. The installer has been posted to the ADuCM350 Product Page on analog.com . Please follow the link for "ADuCM350 Software Development Kit". Registration is required to download.

Question 2

ADuCM350 FAQ Evaluation Kit Software Platform

Accepted Answer

Q: What is the ADuCM350 Evaluation Kit Software Platform (EKSP)? 
 A: The EKSP is GUI based PC software coupled with firmware running on the Eval-ADUCM350EBZ evaluation board which allows the user to easily perform analog front end (AFE) measurements, without having to write any embedded software. The EKSP installer can be downloaded from the ADuCM350 product page free of charge. This installer will install the GUI based PC software. The firmware (aducm350_eksp.hex) can be found in the Firmware folder (if the default installation path is used: C:\Program Files (x86)\Analog Devices\ADuCM350\EKSP\Firmware). 
 Q: I have downloaded the ADuCM350 Support Documentation, but I don't see an EKSP user guide. Is there one available? 
 A: A preliminary version of the EKSP user guide is attached to this FAQ. 
 Q: I have installed the EKSP software and connected the Eval-ADUCM350EBZ motherboard to the PC, but the COM port selection window indicates that there is no ADuCM350 with EKSP connected. Why is the software not connecting to my board? 
 
 A: The ADuCM350 EKSP firmware is not flashed to the ADuCM350 device on the motherboard by default. If you have not already done so, you will need to download the EKSP firmware to the ADuCM350. 
 If you have already successfully downloaded the firmware, but still cannot connect, please check that you have the jumper settings on the motherboard correct, as per the EVAL-ADuCM350EBZ User Guide (UG-668). 
 Q: How do I download the EKSP firmware (aducm350_eksp.hex) to the part/board? 
 A: The following steps assume that both the ADuCM350 Software Development Kit (SDK) and the ADuCM350 EKSP software have been installed. 
 
 Connect the USB-SWD/UART-EMUZ emulator board (not yet connected to the motherboard) to the target PC using the USB cable provided and open Device Manager (can be found in Control Panel) on the PC. Under Ports, the emulator board will be recognized as JLink CDC UART Port (COMX, where X is the COM port number). Take note of the COM port number. 
 Launch the CM3WSD serial downloader tool. This can be found in the tools directory of the SDK installation (if the default installation path is used: C:\Analog Devices\ADuCM350BBCZ\Eval-ADUCM350EBZ	ools\SerialDownloader). 
 Click Browse and navigate to the ADuCM350 EKSP install directory. The aducm350_eksp.hex file can be found in the Firmware folder (if the default installation path is used: C:\Program Files (x86)\Analog Devices\ADuCM350\EKSP\Firmware). 
 Select the Serial Port to which the emulator board is connected (which was noted in 1 above) and set the Baudrate (any baudrate can be used, 115200 is sufficient). 
 Select the Program and Verify Flash Action and connect the emulator board to the motherboard before clicking Start. 
 The Monitor Status window will issue instructions to “Press Download and pulse Reset on hardware”. This implies keeping the SERIAL DOWNLOAD button (S6) on the motherboard depressed while pressing and releasing the RESET button (S5) before releasing the SERIAL DOWNLOAD button. 
 The Monitor Status window will indicate that the download is in process and will request that Reset button is clicked once complete. After clicking Reset in the CM3WSD window, also press reset on the motherboard.

Q: I have performed a measurement and plotted my results. Is it possible to zoom in on the plot? 
 A: Yes. Click the zoom icon in the lower right-hand corner of the plot window for zoom options (see image below). 
 
 Q: Can I save my results to a file for manipulation in another application (e.g. spreadsheet application)? 
 A: Yes. There are 2 methods for saving the data. 
 
 From the main window, in the tab for the particular measurement type, there will be a Save to File button directly under the Measurement Return Data. Click this button to save the measurement data as a tab delimited text file. This can then be opened by/imported into your chosen spreadsheet application or text editor. 
 From the Plot AFE Results window, right click on the plot which has the data you want to save. Select whether your method of exporting the data (see image below).

Q: What is the purpose of the Ideal Impedance values? Do these values impact on the measurement? 
 A: The Ideal Impedance values (see image below) are purely for comparison purposes. If the impedance to be measured is known, the configuration and value(s) can be entered to allow comparison with the measured values. The ideal values have no impact on the measurement or the results, but they do form the basis for the % Magnitude Error and Phase Error values from an Impedance measurement. In the plot window, the measured results are compared to the real results by default, but can be turned off by unchecking the Plot Ideal Values check box. 
 
 Q: Can I read and write to memory mapped registers (MMRs) using the EKSP GUI? 
 A: Yes. The System Tools tab allows the user to read from or write to any available MMR on the ADuCM350. 
 Please note that there are no safety measures around any MMR writes (i.e. the user will not be prevented from writing to any MMR, regardless of the consequences). Writing to certain MMRs may interrupt UART communication between the EKSP GUI and the ADuCM350 and could cause the GUI software to become unresponsive. 
 Q: Can I perform an amperometric/potentiostat measurement using the EKSP software? 
 A: The current version only supports impedance measurements. Other measurement types will be added in future versions. 
 Q: Can I perform an auxilliary channel measurement using the EKSP software? 
 A: The current version only supports impedance measurements. Other measurement types will be added in future versions. 
 Q: Can I perform an CapTouch measurements using the EKSP software? 
 A: The current version only supports impedance measurements. Other measurement types will be added in future versions. 
 Q: I would like to communicate with the EKSP firmware from my own PC application. How do I communicate with it? Is the UART protocol which is used available? 
 A: The EKSP UART Protocol document is attached to this FAQ.

Attachments:

ez.analog.com/.../ADuCM350_5F00_EKSP_5F00_UART_5F00_Protocol_5F00_1_5F00_1518.pdf

ez.analog.com/.../ADuCM350_5F00_EvaluationKitSoftwarePlatform_5F00_PrD.pdf

Question 3

Known Issues for ADuCM350 Silicon and Support Material

Accepted Answer

ADuCM350 Known Silicon Issues 
 
 ADuCM350 V1.4 silicon will release in March 2016. The change from V1.2 to V1.4 is a minor metal edit to improve the robustness of the high frequency, internal RC oscillator (HFOSC). Both MAN_ID and CHIP_ID information will be updated as part of this change.

Issue 
 Description 
 Workaround(s)

VBACK domain leakage 
 Excessive leakage on VBACK domain when in use as backup supply. 
 No solution available. It is recommended not to use SuperCap/VBACK mode.

UPLL pre-charging requirement 
 UPLL must ne pre-charged before being used. 
 SDK Version 2.4+ includes extra lines of code when using the UPLL to pre-charge the VCO loop.

High frequency crystal (HFXTAL) and duty cycle correction (DCC) block 
 It has been found that when the HFXTAL and DCC block are used as the root clock source, it is sensitive to digital noise. 
 Always use the system PLL (SPLL) as the root clock when the HFXTAL is source.

System PLL and USB PLL (SPLL/UPLL) Status Bit 
 The SPLL/UPLL status bit threshold is too low and can cause the SPLLUNLOCK / UPLLUNLOCK bit to set when it is locked. 
 Use SPLL / UPLL lock bit(s) (SPLLLOCK / UPLLLOCK) to reliably determine when the PLL is locked initially. Do not use SPLLUNLOCK / UPLLUNLOCK bit as a reliable indicator that the PLL has lost lock.

ADuCM350 Datasheet 
 
 In Rev.A of the ADuCM350 datasheet, there is an error in Figure 31 and Figure 32 . For both figures, the Z value is incorrect. It should read: 
 Z = 140Ω + 68nF 
 Also, the Y-axis label should read: 
 Number of Measurements 
 The same corrections apply to both Figure 31 and Figure 32. It should also be noted that the capacitors used for these measurements (including the accuracy measurements in Figures 29 and 30) were COG capacitors with 1% tolerance. This tolerance may cause a slight deviation from the ideal value.

I2C Block 
 
 Full I2C errata document available here .

Issue 
 Description 
 Workaround(s)

I2C bus hangs when configured as slave Tx 
 During a read from the master to slave, if the slave’s FIFO is empty, the slave should NACK the master’s request. Then it should release the bus allowing the master to generate a STOP condition. In the case of the slave’s FIFO buffer being empty, if data is loaded when the ninth SCL clock is high, the slave generates an ACK to the master and the MSB of read data is sent on the following SCL positive edge. If the MSB is 0, the SDA line will be held low and the slave will wait for extra SCL clocks to transmit the remaining bits. When this happens, the I2C master detects a NACK and then generates a STOP condition. Master arbitration is lost due to the SDA line being indefinitely low.

Placing valid data in the Slave Tx FIFO. 
 Set the BUS_CLR_EN bit in the I2CMCON register. If this bit is set, the master will initiate a Bus-Clear operation by sending up to 9 extra SCL cycles. 
 Set EARLYTXR bit in the I2CSCON register. Setting this bit enables a transmit request just after the positive edge on the SCL line during the read bit transmission. 
 Resetting the slave interface by disabling/enabling the slave.

I2C master fails to operate when the sum of the values in HIGH and LOW in the I2CDIV register has a value of less than 18 (0x12) 
 In an attempt to minimize the power consumption of the I2C interface, it may be desirable to set the PCLK frequency to 1MHz and set the SCL frequency to 100kHz. Using the provided formula, this would lead to the following HIGH and LOW values in the I2CDIV register: HIGH = (REQD_HIGH_TIME / PCLK_PERIOD) – 2 HIGH = ((10us / 2) / 1us) – 2 HIGH = 3 LOW = (REQD_LOW_TIME / PCLK_PERIOD) – 1 LOW = ((10us / 2) / 1us) – 1 LOW = 4 When these values are programmed, the I2C master will not function.

Use the adi_I2C_SetMasterClock() function to set the SCL frequency. Ensure to check for a valid return code. 
 Do not program values to the HIGH and LOW fields in the I2CDIV register which give a sum of less than 18 (0x12).

I2C slave hangs the I2C bus when clock stretching is enabled 
 Clock stretching is an I2C feature that allows a slave device to temporarily pause communication by holding SCL low (for example, a slave device receives a READ request from a Master but, its Transmit FIFO is empty). Clock stretching is enabled setting the STRETCHSCL bit in the I2CSCON register to 1. If this is done on the rising edge of SCL a glitch can occur. Other devices might interpret this as a real clock pulse and it could cause the bus to hang. 
 It is recommended that the clock stretching feature is not used.

Software Development kit.

Example 
 Version 
 Issue 
 Resolution

AFE_Examples 
 SDK 2.3.0.0 
 The workspace file, AFE_Examples.eww is missing from the AFE_Examples folder. 
 This workspace was intended to allow all of the AFE example projects to be opened in a single workspace. Each of the examples are still present and functional. The workspace file (AFE_Examples.eww) is attached to this document.

Current Profiling 
 SDK 2.2.0 
 Lack of Readme 
 Refer to AN-1282 Application Note in Documentation Folder.

Captouch_5ButtonsTest 
 SDK 2.2.0 
 “Right” and “Left” buttons do not work 
 These pads are used as external interrupts on board. Remove R63 and R65. See Eval-ADuCM350 motherboard schematic for details.

Captouch_5ButtonsTest 
 SDK 2.2.0 
 UART Comms Does not work 
 The simplest fix is to call “test_Init()” after “adi_initpinmux()” instead of before . Baud Rate is 9600.

gpio_test, GpioTest,ThreadSpi. 
 SDK 2.2.0 
 Lack of Readme 
 M5 needs to be connected for VDD_IO supply. LK14 needs to be inserted for VLCD_VDD supply. Reveiew Pin-Out for GPIO supplies

Mipi_SSD1963_Test 
 SDK 2.2.0 
 No Hardware 
 This display has been discontinued by supplier. Code is just for reference only.

AmperometricMeasurement 
 SDK 2.2.0 
 No option to change the value of RCAL or RTIA in software. 
 The functions to set the values of RCAL and RTIA are available in afe.c. See the Amperometric Measurement FAQ for instructions on how to use them and where to insert them. https://ez.analog.com/docs/DOC-11063

Attachments:

ez.analog.com/.../4743.AFE_5F00_Examples.eww.zip

Question 4

ADuCM350 FAQ Potentiostat / Amperometric

Accepted Answer

Q: I would like to use the ADuCM350 to do potentiostat type measurements ? 
 A: Please refer to AN-1281 and the Amperometric example code in the Software Development Kit. Details in Featured Content on ADuCM350 Engineerzone homepage. 
 Q: Can I put a +200mV step on sensor ? See AN-1281+ details n Featured Content on ADuCM350 Engineerzone homepage. 
 A: Yes. At time=0, the system is calibrated so that no voltage across sensor (both sides precisely calibrated to 1.1V). 
 At time=1, the DAC can output 1.3V to give a DC step across sensor of 200mV. 
 Q: I have changed RCAL/RTIA on my board, how do I reflect this change in the Amperometric Measurement example from the SDK? 
 A: Please refer to the following: https://ez.analog.com/docs/DOC-11063

Question 5

New Revision of UG-587 Available

Accepted Answer

A new revision of the ADuCM350 Hardware Reference Manual is available for download from the ADuCM350 product page on analog.com . The changes from Rev.A to Rev.B are shown in the Revision History section.

Question 6

AFE Transmit Stage

Accepted Answer

How does the ADuCM350 set a voltage on the sensor ? 
 First step is to consider the DAC and it's transfer function.
 
 The VDAC Output Range is 0.2V to 1.0V.

This signal is then biased and gain up to produce the output voltage from the Excitation Amplifier, VD, which is the voltage seen by the sensor. 
 VD = ( ( VD-0.6V ) X 2 ) + VBIAS
 
 VDAC is referenced to the INAMP reference of 0.6V 
 The Excitation/INAMP Loop has a gain of 2. 
 VBIAS: The Common Mode of the System is setup by the +ve terminal of the TIA.

This leads to a transmit channel transfer function that looks like: 
 
 How does the TIA set the Common Mode of the AFE Measurement Loop ? 
 See diagram below as reference.

Assume 2-Wire Measurement with P and N tied internally. 
 
 In 4-Wire, Raccess would be automatically compensated for on D/P/N and T.

TIA Sets Common Mode 
 
 Positive terminal of the TIA is connected to VBIAS. 
 Therefore the negative terminal of TIA forced to VBIAS. This is a Virtual Ground.

T = N = VBIAS 
 
 T and N are shorted internally

Excitation Buffer Forces D so that P &ndash; N = 0V 
 
 But N is forced to VBIAS by TIA 
 So Excitation Buffer drives P to = VBIAS

Hence D is forced to have a common mode of VBIAS 
 
 With the DAC at midscale, the Excitation Buffer output sits at VBIAS

Example Calculation: Sensor needs to see +450mV on Counter and 0V on Working Electrode. i.e +450mV step across Sensor. 
 Goal is to have P &ndash; N = +450mV 
 
 Assume VBIAS = 1.1V. 
 T = 1.1V = Virtual Ground 
 Given that N = T = VBIAS, this implies that the voltage at the P node needs to be 1.55V

Signal swing of Excitation Amplifier output is -800mV to +800mV 
 Dividing this range by the resolution of the DAC 
 
 1.6V / 2^12 = 390.725&micro;V 
 Therefore each DAC LSB is equivalent to 390.725&micro;V out of the Excitation Amplifier 
 Midscale of the DAC is equivalent to a 0V difference between P and N 
 Midscale DAC code = 2048 = 0x800

450mV / 390.725&micro;V = 1152 = 0x480 
 1,1V + 450mV = 0x800 + 0X480 = 0xC80 
 Therefore, the DAC code required for a +450mV step on the sensor is 0xC80

Question 7

ADuCM350 FAQ SDK Driver Specific FAQs

Accepted Answer

AFE Driver 
 Q: The v2.2.0 SDK AFE driver (afe.c) has interrupt handlers for the Command FIFO interrupt (AFE_CmdFIFO_Int_Handler) and the Data FIFO interrupt (AFE_DataFIFO_Int_Handler), but not for the Generate or Capture interrupts. Are there handlers available for the Generate and Capture interrupts? 
 A: The v2.3.X SDK is currently under development (at time of print, 11 Feb 2015). The AFE driver in this new revision of the SDK will handle Generate and Capture interrupts and will introduce a new function which can register a callback for any of the 4 AFE interrupts. Preliminary code for the Generate and Capture interrupts and the register callback function are below for reference ahead of the v2.3.X SDK release. 
 /* ANALOG_CAPTURE_INT handler */ 
 ADI_INT_HANDLER(AFE_Capture_Int_Handler) { 
 /* Only 1 instance of the AFE in the system */ 
 ADI_AFE_DEV_HANDLE hDevice = pAFE_DevData; 
 uint32_t sources; 
 uint32_t enables; 
 uint32_t clear = 0; 
 uint32_t disable = 0; 
 sources = hDevice->pAFE->AFE_ANALOG_CAPTURE_INT; 
 enables = hDevice->pAFE->AFE_ANALOG_CAPTURE_IEN; 
 /* Interrupt bit: ADC_RESULT_READY */ 
 if ((sources & BITM_AFE_AFE_ANALOG_CAPTURE_INT_ADC_RESULT_READY) && 
 (enables & BITM_AFE_AFE_ANALOG_CAPTURE_IEN_ADC_RESULT_READY_IEN)) { 
 /* Schedule interrupt to be cleared */ 
 clear |= BITM_AFE_AFE_ANALOG_CAPTURE_INT_ADC_RESULT_READY; 
 } 
 /* Interrupt bit: DFT_RESULT_READY */ 
 if ((sources & BITM_AFE_AFE_ANALOG_CAPTURE_INT_DFT_RESULT_READY) && 
 (enables & BITM_AFE_AFE_ANALOG_CAPTURE_IEN_DFT_RESULT_READY_IEN)) { 
 /* Schedule interrupt to be cleared */ 
 clear |= BITM_AFE_AFE_ANALOG_CAPTURE_INT_DFT_RESULT_READY; 
 } 
 /* Interrupt bit: SUPPLY_LPF_RESULT_READY */ 
 if ((sources & BITM_AFE_AFE_ANALOG_CAPTURE_INT_SUPPLY_LPF_RESULT_READY) && 
 (enables & BITM_AFE_AFE_ANALOG_CAPTURE_IEN_SUPPLY_LPF_RESULT_READY_IEN)) { 
 /* Schedule interrupt to be cleared */ 
 clear |= BITM_AFE_AFE_ANALOG_CAPTURE_INT_SUPPLY_LPF_RESULT_READY; 
 } 
 /* Interrupt bit: TEMP_RESULT_READY */ 
 if ((sources & BITM_AFE_AFE_ANALOG_CAPTURE_INT_TEMP_RESULT_READY) && 
 (enables & BITM_AFE_AFE_ANALOG_CAPTURE_IEN_TEMP_RESULT_READY_IEN)) { 
 /* Schedule interrupt to be cleared */ 
 clear |= BITM_AFE_AFE_ANALOG_CAPTURE_INT_TEMP_RESULT_READY; 
 } 
 /* Interrupt bit: ADC_MIN_FAIL */ 
 if ((sources & BITM_AFE_AFE_ANALOG_CAPTURE_INT_ADC_MIN_FAIL) && 
 (enables & BITM_AFE_AFE_ANALOG_CAPTURE_IEN_ADC_MIN_FAIL_IEN)) { 
 /* Since this is typically an error condition, we don't care if there is one */ 
 /* or multiple interrupts, so schedule interrupt to be disabled. */ 
 disable |= BITM_AFE_AFE_ANALOG_CAPTURE_IEN_ADC_MIN_FAIL_IEN; 
 } 
 /* Interrupt bit: ADC_MAX_FAIL */ 
 if ((sources & BITM_AFE_AFE_ANALOG_CAPTURE_INT_ADC_MAX_FAIL) && 
 (enables & BITM_AFE_AFE_ANALOG_CAPTURE_IEN_ADC_MAX_FAIL_IEN)) { 
 /* Since this is typically an error condition, we don't care if there is one */ 
 /* or multiple interrupts, so schedule interrupt to be disabled. */ 
 disable |= BITM_AFE_AFE_ANALOG_CAPTURE_IEN_ADC_MAX_FAIL_IEN; 
 } 
 /* Interrupt bit: ADC_DELTA_FAIL */ 
 if ((sources & BITM_AFE_AFE_ANALOG_CAPTURE_INT_ADC_DELTA_FAIL) && 
 (enables & BITM_AFE_AFE_ANALOG_CAPTURE_IEN_ADC_DELTA_FAIL_IEN)) { 
 /* Since this is typically an error condition, we don't care if there is one */ 
 /* or multiple interrupts, so schedule interrupt to be disabled. */ 
 disable |= BITM_AFE_AFE_ANALOG_CAPTURE_IEN_ADC_DELTA_FAIL_IEN; 
 } 
 /* Check if there is a callback defined */ 
 if (hDevice->cbCaptureFcn) { 
 /* Call the function if the interrupt is watched */ 
 /* Need to check both interrupts scheduled to be cleared */ 
 /* and interrupts scheduled to be disabled to find out */ 
 /* what interrupt caused this ISR to be entered */ 
 if ((clear | disable) & hDevice->cbCaptureWatch) { 
 /* Passing to the callback the bits scheduled for clear or disable */ 
 hDevice->cbCaptureFcn(hDevice, 0, NULL); 
 } 
 } 
 adi_AFE_EnableInterruptSource(hDevice, ADI_AFE_INT_GROUP_CAPTURE, disable, false); 
 adi_AFE_ClearInterruptSource(hDevice, ADI_AFE_INT_GROUP_CAPTURE, clear); 
 } 
 /* ANALOG_GEN_INT handler */ 
 ADI_INT_HANDLER(AFE_Generate_Int_Handler) { 
 /* Only 1 instance of the AFE in the system */ 
 ADI_AFE_DEV_HANDLE hDevice = pAFE_DevData; 
 uint32_t sources; 
 uint32_t enables; 
 uint32_t clear = 0; 
 sources = hDevice->pAFE->AFE_ANALOG_GEN_INT; 
 enables = hDevice->pAFE->AFE_ANALOG_GEN_IEN; 
 /* Interrupt bit: DELAY_COMMAND_DONE */ 
 if ((sources & BITM_AFE_AFE_ANALOG_GEN_INT_DELAY_COMMAND_DONE) && 
 (enables & BITM_AFE_AFE_ANALOG_GEN_IEN_DELAY_COMMAND_DONE_IEN)) { 
 /* Schedule interrupt to be cleared */ 
 clear |= BITM_AFE_AFE_ANALOG_GEN_INT_DELAY_COMMAND_DONE; 
 } 
 /* Interrupt bit: HARDWARE_SETUP_DONE */ 
 if ((sources & BITM_AFE_AFE_ANALOG_GEN_INT_HARDWARE_SETUP_DONE) && 
 (enables & BITM_AFE_AFE_ANALOG_GEN_IEN_HARDWARE_SETUP_DONE_IEN)) { 
 /* Schedule interrupt to be cleared */ 
 clear |= BITM_AFE_AFE_ANALOG_GEN_INT_HARDWARE_SETUP_DONE; 
 } 
 /* Interrupt bit: BREAK_SEQUENCE_ORG */ 
 if ((sources & BITM_AFE_AFE_ANALOG_GEN_INT_BREAK_SEQUENCE_ORG) && 
 (enables & BITM_AFE_AFE_ANALOG_GEN_IEN_BREAK_SEQUENCE_ORG_IEN)) { 
 /* Schedule interrupt to be cleared */ 
 clear |= BITM_AFE_AFE_ANALOG_GEN_INT_BREAK_SEQUENCE_ORG; 
 } 
 /* Interrupt bit: CUSTOM_INT */ 
 if ((sources & BITM_AFE_AFE_ANALOG_GEN_INT_CUSTOM_INT) && 
 (enables & BITM_AFE_AFE_ANALOG_GEN_IEN_CUSTOM_INT_IEN)) { 
 /* Schedule interrupt to be cleared */ 
 clear |= BITM_AFE_AFE_ANALOG_GEN_INT_CUSTOM_INT; 
 } 
 /* Check if there is a callback defined */ 
 if (hDevice->cbGenerateFcn) { 
 /* Call the function if the interrupt is watched */ 
 /* Need to check both interrupts scheduled to be cleared */ 
 /* and interrupts scheduled to be disabled to find out */ 
 /* what interrupt caused this ISR to be entered */ 
 if (clear & hDevice->cbGenerateWatch) { 
 /* Passing to the callback the bits scheduled for clear or disable */ 
 hDevice->cbGenerateFcn(hDevice, 0, NULL); 
 } 
 } 
 adi_AFE_ClearInterruptSource(hDevice, ADI_AFE_INT_GROUP_GENERATE, clear); 
 } 
 /*! 
 * @brief Application callback registration for AFE interrupt handlers. 
 * 
 * @param[in] hDevice Device handle obtained from adi_AFE_Init(). 
 * @param[in] group AFE interrupt group type identifier. 
 * @param[in] cbFunc Application callback address; the function to call. 
 * @param[in] cbWatch The interrupts to watch, controlling which interrupts result in a callback. 
 * 
 * @return Status 
 * - #ADI_AFE_SUCCESS Call completed successfully. 
 * - #ADI_AFE_ERR_BAD_DEV_HANDLE Invalid device handle. 
 * - #ADI_AFE_ERR_NOT_INITIALIZED Device not initialized. 
 * - #ADI_AFE_ERR_ACLKOFF ACLK disabled from the clock gate. 
 * - #ADI_AFE_ERR_WRONG_ACLK_FREQUENCY Programmed ACLK frequency is not the required 16MHz. 
 * - #ADI_AFE_ERR_CALLBACK_OVERWRITE Attempt to overwrite existing callback. 
 * 
 * @details Registers an application-defined callback function with one of the AFE interrupt handlers. 
 * Callbacks are made in response to received AFE interrupts, depending on whether they are enabled 
 * and whether the corresponding callback watch bits are set. This allows the application to control which 
 * interrupts it wants to be called back on. 
 * The callback to the application is made in context of the originating interrupt (i.e. the AFE 
 * interrupt handler that is registered in the system's interrupt vector table). Extended processing 
 * during the callback (an extension of the AFE interrupt handler) is discouraged so as to avoid lower-priority 
 * interrupt blocking. Also, any register read-modify-write operations should be protected using the 
 * ADI_ENTER_CRITICAL_REGION()/ADI_EXIT_CRITICAL_REGION() pair to prevent higher-priority interrupts from modifying 
 * said register during the read-modify-write operation. 
 * 
 * @note CALLBACKS: AFE interrupt callbacks are \a disabled by default during the API initialization (#adi_AFE_Init()). 
 * The application may use the #adi_AFE_RegisterCallback() API to register an application-defined 
 * callback function with the interrupt handler that will be called in response to selected AFE interrupts. 
 * The callback registration API takes an interrupt mask (of type uint32_t) that designates the set of interrupts 
 * to watch (upon which to dispatch the callback). When any of the watched interrupts occur, the appropriate AFE 
 * interrupt handler will make the callback to the application for application-based interrupt handling. The application 
 * callback should \a avoid \a extended \a processing during the callback as the callback is made context of the initiating 
 * interrupt and will block lower-priority interrupts. If extended application-level interrupt processing is required, the 
 * application should schedule it for the main application loop and exit the callback as soon as possible.

* 
 */ 
 ADI_AFE_RESULT_TYPE adi_AFE_RegisterAfeCallback(ADI_AFE_DEV_HANDLE hDevice, ADI_AFE_INT_GROUP_TYPE group, ADI_CALLBACK cbFunc, uint32_t cbWatch) { 
 ADI_AFE_RESULT_TYPE result = ADI_AFE_SUCCESS; 
 #ifdef ADI_DEBUG 
 if (adi_AFE_InvalidHandle(hDevice)) { 
 return ADI_AFE_ERR_BAD_DEV_HANDLE; 
 } 
 if (adi_AFE_HandleNotInitialized(hDevice)) { 
 return ADI_AFE_ERR_NOT_INITIALIZED; 
 } 
 if (pADI_SYSCLK->CLKCON5 & BITM_SYSCLK_CLKCON5_ACLKOFF) { 
 return ADI_AFE_ERR_ACLKOFF; 
 } 
 if (16000000 != SystemGetClockFrequency(ADI_SYS_CLOCK_ACLK)) { 
 return ADI_AFE_ERR_WRONG_ACLK_FREQUENCY; 
 } 
 
 if (!((ADI_AFE_INT_GROUP_CAPTURE == group) || (ADI_AFE_INT_GROUP_GENERATE == group) || (ADI_AFE_INT_GROUP_CMD_FIFO == group) || (ADI_AFE_INT_GROUP_DATA_FIFO == group))) { 
 return ADI_AFE_ERR_INVALID_IRQ; 
 } 
 if ((cbFunc && hDevice->cbCaptureFcn) || (cbFunc && hDevice->cbGenerateFcn) || (cbFunc && hDevice->cbCmdFifoFcn) || (cbFunc && hDevice->cbDataFifoFcn)) { 
 return ADI_AFE_ERR_CALLBACK_OVERWRITE; 
 } 
 #endif 
 switch (group) 
 { 
 case ADI_AFE_INT_GROUP_CAPTURE: 
 hDevice->cbCaptureFcn = cbFunc; 
 hDevice->cbCaptureWatch = cbWatch; 
 break; 
 case ADI_AFE_INT_GROUP_GENERATE: 
 hDevice->cbGenerateFcn = cbFunc; 
 hDevice->cbGenerateWatch = cbWatch; 
 break; 
 case ADI_AFE_INT_GROUP_CMD_FIFO: 
 hDevice->cbCmdFifoFcn = cbFunc; 
 hDevice->cbCmdFifoWatch = cbWatch; 
 break; 
 case ADI_AFE_INT_GROUP_DATA_FIFO: 
 hDevice->cbDataFifoFcn = cbFunc; 
 hDevice->cbDataFifoWatch = cbWatch; 
 break; 
 } 
 
 return result; 
 }

Question 8

First Steps: Quick Measurement with Eval-ADuCM350 & EKSP Labview GUI

Accepted Answer

The following is a short easy guide to get an Impedance measurement plotted on your PC on receipt of the ADuCM350 evaluation kit, the Eval-ADuCM350EBZ. 
 The EKSP is GUI based PC software coupled with firmware running on the Eval-ADUCM350EBZ evaluation board which allows the user to easily perform analog front end (AFE) measurements, without having to write any embedded software. 
 This process assumes you have not downloaded new code on to part or erased the EKSP.hex file that has been downloaded to the ADuCM350 by default. Please go to ADuCM350 FAQ Evaluation Kit Software Platform if you need to re-download EKSP.hex file. 
 Step 1. Download EKSP Labview GUI Software 
 The EKSP installer can be downloaded from the ADuCM350 Design Resources Downloads. This installer will install the GUI based PC software. 
 Step 2. Connect Eval-ADuCM350EBZ board to PC 
 Once the software is installed, connect the emulator board (not yet connected to the motherboard) to the target PC using the USB cable provided and open Device Manager (can be found in Control Panel) on the PC. Under Ports, the emulator board will be recognized as JLink CDC UART Port (COMX, where X is the COM port number). Take note of the COM port number. 
 Please ensure the Switch Mux Config Board is mounted correctly on the Eval-ADuCM350EBZ board as shown below. 
 
 Step 2. Run EKSP Labview GUI 
 Launch the ADuCM350 EKSP GUI software. ADuCM350_EKSP.exe can be found in the Start menu under All Programs -> Analog Devices -> ADuCM350 or in the installation directory (if the default installation path is used: C:\Program Files (x86)\Analog Devices\ADuCM350). 
 The software will automatically detect the available COM ports and connect with the board. If more than one board is detected, the user will have the option of which board to connect to. 
 
 If the software fails to connect, try some or all of the following: 
 
 Ensure that the USB-SWD/UART-EMUZ emulator board is connected to the PC and to the Eval-ADUCM350EBZ motherboard 
 Reset the Eval-ADUCM350EBZ motherboard 
 Check that the links on the Eval-ADUCM350EBZ motherboard are in the correct (default) positions see UG-668 in Design Documentation folder. 
 
 Step 3. Quick Impedance Measurement (Frequency Sweep) 
 Once GUI Opens: 
 
 Click Go 
 Click Plot 
 
 By default, the ADuCM350 EKSP software is configured to do a frequency sweep impedance measurement, just by clicking Go . The default values will trigger multiple impedance measurements, each with an AC excitation voltage amplitude of 6.36 mV and frequencies from 1 kHz to 50 kHz in 1 kHz steps. 
 
 While the measurements are being performed, the mouse cursor will change to the system busy cursor and the Impedance Measurement Status LED will light. Once the measurements are complete, the LED will extinguish and Measurement Return Data will be populated with results. 
 To view a simple plot of the results, click the Plot button below the results and a plot will open in a separate window, as shown in Figure 6. Click Plot on both the ADuCM350 EKSP Tab and again on the Plot AFE Results Tab, to plot the values specified in the Plot Selection drop down menu (Impedance Magnitude vs. Frequency by default). Alternative plotting options can be found in the Plot Selection drop down menu. Click Close to close this window. 
 The default plot below is a Measured Versus Theoretical Impedance Frequency Sweep. 
 
 For more information on the EKSP Labview GUI and how to used it please refer to 
 ADuCM350 FAQ Evaluation Kit Software Platform which is an FAQ and has a link to the EKSP Userguide.

Question 9

ADuCM350 FAQ Power Management Unit

Accepted Answer

1. Are there details available on power consumption during various power modes? 
 >> Please refer to AN-1282 for details 
 2. Do I need to explicitly disable a module/peripheral when not used in order to save power? 
 >> No. The modules are automatically clock gated when no accesses are made to them. Please refer to HRM for more details. 
 3. Can I execute instructions when part is in CORE_SLEEP mode? 
 >> No instructions can be executed; however, DMA transfers can continue to happen between peripherals and memories.

Question 10

ADuCM350 FAQ Real Time Clock (RTC)

Accepted Answer

Q: The RTC chapter of the HRM (UG-587) mentions a "1 Hz domain". Is this a typo or is there in fact a 1 Hz domain? 
 A: The references to "1 Hz domain" really mean the "32 kHz clock domain in which 1 Hz real-time counting and prescaling is carried out". The 32 kHz clock is prescaled down to 1 Hz and the integer part of the RTC updates at a rate of 1 Hz, but all such operations (prescaling and counting) are synchronous to 32 kHz. Synchronisation is to and from the 32 kHz clock (LFXTAL).

Question 11

ADuCM350 FAQ System Integrity

Accepted Answer

Q: Is there any detail on System Integrity of device ? 
 A: Please refer to apps note AN-1263 in Design Documentation. 
 Q: How do I tell the embedded microkernel to check the integrity of flash page 0? 
 A: By default the embedded microkernel checks the integrity of Flash page 0. This can be bypassed by writing 0xFFFFFFFF at address 0x7FC. Please refer to <M350 security app note> for further information. 
 Q: How can I disable the JTAG port in my application? Can I guarantee no unauthorized access to the JTAG even before my application runs? 
 A: On reset, JTAG/Serial Wire access to the ADuCM350 is disabled while the embedded microkernel is running. On finishing running the kernel, JTAG/Serial Wire access is enabled and execution of user code starts. The application code can immediately disable the JTAG/Serial Wire access, however there is a short period of time when the JTAG/Serial Wire access is enabled and unauthorized third party access is technically possible. 
 This can be avoided by writing 0x16032010 at address 0x5FFE8. This guarantees the kernel will not enable JTAG/Serial Wire access when finishing execution, and JTAG/Serial Wire access is still disabled when the application code is executed. It is possible to enable JTAG/Serial Wire access from the application code if desired.

Question 12

ADuCM350 FAQ GP Timers

Accepted Answer

Q. What is the reference clock for the GP Timers? 
 A: 
 
 The clock source for GP Timers can be HF_CLK,PCLK,LF_CLK or LF_XTAL which is programmable. 
 T he GP timer modules can get starved of clock if the clock source mux is set to a clock that is not (or no longer) present. In that state, the mux cannot be changed back (timer domain never synchronizes). To avoid this, always check clock status before setting timer mux to anything other than PCLK and then set mux back to PCLK before disabling the timer after its use. 
 
 Q. What are the operating modes available with the timers? 
 A: The timers can operate in Free running or periodic mode. In free running mode, the counter increments/decrements from the minimum/maximum value until full/zero scale and starts again. In periodic mode, it starts from the value in the GPTLD MMR until zero/full scale. 
 The timers also provide PWM function and can also capture 16 interrupt event functions.

Question 13

Bioimpedance Measurement Using ADuCM350

Accepted Answer

Setup 
 Note this is an example "reference" to setup the ADuCM350 for 4-Wire Skin impedance measurements. 
 4-Wire measurements are for Absolute Accuracy and the ADuCM350 requires an external In-Amp. 
 For Relative measurements, the ADuCM350 can operate as a single chip solution. 
 Review AN-1302 for the differences between 2-Wire Skin Impedance and 4-Wire Skin Impedance. AN-1271 is useful to optimize the ADuCM350 Impedance engine for optimal performance. 
 
 Documentation: AN-1302, and Configuring ADuCM350-BIO3Z board for 50kHz Bio-Impedance Measurement.pdf

Hardware 
 
 Eval-ADuCM350EBZ (LK1 is in place) 
 ADuCM350 4Wire Bio Config 3 (Eval-ADuCM350BIO3Z) board. (LK7, LK8, LK9, LK10 in place; LK16, LK17, LK18, and LK19 in position B)

Software 
 
 ImpedanceMeasurement_4WireBioIsolated_BodyComp example in IAR Embedded Workbench 
 
 View data in Comms port / Terminal IO (Check SDK Userguide in document folder for details).

Note: When performing the Bio-Impedance measurement on the body, please ensure the laptop is unplugged from the power source as an additional precaution. 
 SDK Download /Debug and Collect Data 
 
 Download and Debug Code 
 
 A s Per SDK Quickstart UG-677 
 
 In default mode 1.5KOhm is selected. 
 
 See 4-Wire Bio Config 3 schematic and layout. 
 
 Theory / System connections documented in detail on AN-1302 apps note 
 Once Code is Download -> Run Code and view data in Terminal I/O or UART. 
 Should get results below out of box for default settings.

Validate Results 
 
 Hardware Change: Connect LK16, LK17, LK 18, and LK19 in position A. insert USB-mini Cable, stripped at the other end, and connect the impedance to be measured at the stripped end. 
 Repeat Measurement. 
 
 Hit Reset and then Run buttons 
 You should see impedance connected in the stripped end of the USB-mini cable in results display.

Data View 
 The raw DFT complex results (real and imaginary parts) and the final calibrated unknown impedances (represented in polar coordinates; magnitude and phase) are reported through the UART/STDIO. The USE_UART_FOR_DATA macro determines whether the results are returned to the UART or STDIO. 
 To return data using the UART, set the macro USE_UART_FOR_DATA = 1 (this is the default option). 
 To return data using STDIO, set the macro USE_UART_FOR_DATA = 0.

Attachments:

ImpedanceMeasurement_4WireBioIsolated_BodyComp.zip

3113.attachment.pdf

BIO3ZBoardSchematic.pdf

Question 14

4Wire-Isolated-Bioimpedance ADuCM350 Connections To Sensor

Accepted Answer

4-Wire-Bio-Config 3 Board 
 
 Used to measure a matrix of ideal R and C components. 
 Has built in USB-micro connector to measure &ldquo;real world&rdquo; sensors. 
 Please refer to 4-Wire Bio Config 3 Layout and Schematic in Design Documentation folder when evaluating and modifying board. 
 
 Step 1: Validate Board with Software 
 
 Measure 1.5K (1% accurate) resistor 
 
 Insert following Links:LK7,LK8,Lk9,LK10 
 Insert Links LK16, LK17, LK18, and LK19 on Position B.

Step 2: Electrode Hook Up 
 
 Using the &ldquo;4-Wire Bio Config 3 &rdquo; board, insert a USB-micro cable with stripped end on the other side. 
 
 Rlimit resistor and Isolation capacitors will need to be maintained in signal chain to meet IEC standards.

Raccess will need to be removed from measurement.

Insert following Links: LK7,LK8,Lk9,LK10. 
 Insert following Links on Position A: LK16,LK17,Lk18,LK19. 
 
 4-Wire-Isolated Electrode Configuration 
 Block Diagram 
 Insert following Links: LK7, LK8, LK9 and LK10. 
 
 Board Pictures

Question 15

ADuCM350 FAQ Operational Supply Range / Power Supplies

Accepted Answer

Q: What is the operational voltage range for the ADuCM350 ? 
 A: 
 The digital platform operates from 2.0V to 3.6V. The Digital LDO (High Power LDO) that supplies the digital domain operates to 2.0V. 
 The AFE is characterised and guaranteed from 2.5V to 3.6V. 
 In Back-Up mode - see Power Supplies Chapter in UG-587 - the part will operate down to 1.62V. 
 Q: What type of power management capability is on chip ? 
 A:Please review Power supplies chapter and Power Management chapter in product userguide UG-587 for details. It is designed to operate with direct connections to a battery - can handle battery insertion / battery removal etc.

Question 16

ADuCM350 FAQ AFE Sequencer

Accepted Answer

Q: How do I start writing an AFE squence ? 
 A: Advise to use the example sequences in the Software Development Kit as a reference, e.g. ImpedanceMeasurement_2wire.c 
 Then use the ADuCM350 ASH (AFE Sequence Helper) Tool to modify the sequence. 
 Link to ADuCM350 ASH : ADuCM350 ASH Tool (v1.0).

Q: Details on how to program the sequencer ? 
 A: 
 
 AN-1293 in Design Support Package - A Quick Guide to the ADuCM350 Sequencer. 
 Examples in Analog Front End Interface Chapter of Product Userguide. UG-587. 
 Use the ADuCM350 AFE Sequence Helper tool (see above). 
 
 Q: How deep / how many steps are available in Sequencer ? 
 A: Used correctly there is no limit to the sequncer depth ? If you feel adventurous you can feed it in commands from external memory. 
 Q: How are sequences for the AFE sequencer represented in software? 
 A: The afe_sequences.h file in the Software Development Kit (SDK) contains a number of example sequences. Each sequence is represented by an array of unsigned, 32-bit numbers in hexadecimal format. Each array consists of 2 pieces; the Safety Word and the sequence itself. 
 The first element (element [0]) of any example sequence array is the Safety Word. This is NOT part of the sequence itself. It is used to check the integrity of the sequence that has been executed. The upper half-word (bits[31:16]) contains the command count. This indicates how many commands the sequence comprises of. Note that this does NOT include the Safety Word. Each time the sequencer executes a sequence, the value in the AFE_SEQ_COUNT register is incremented by 1. When the sequence has finished executing, this value should match the command count element of the Safety Word. 
 The lowest byte (bits[7:0]) contains the CRC of the sequence. The CRC algorithm used is CRC-8, using the polynomial x8 + x2 + x + 1, with a seed of 1. There is a function in afe.c called crc8 which performs the calculation and mirrors the ADuCM350 hardware exactly. There is also an appendix in AN-1293 with instructions on how to use a Python CRC calculator (which is available online). Note that the CRC calculation should NOT include the Safety Word. The sequencer performs a CRC calculation on the sequences that it executes and returns the result to the AFE_SEQ_CRC register. This value should match the CRC element of the Safety Word. 
 Q: How are sequences triggered by the software? 
 A: The AFE driver (afe.c) in the SDK contains a function called adi_AFE_RunSequence which illustrates how a sequence can be triggered in software. It should be noted that this function is not optimised for performance and may not be suited to all applications, in particular where the core is required to perform other tasks while the sequencer is running. adi_AFE_RunSequence is a function which does a number of things, but remember that all of these tasks are executed on the core, the sequencer is a separate piece of hardware. First it initializes the sequencer (adi_AFE_SeqInit), pointing to the sequence to be run (txbuffer), where to put the results (rxbuffer) and how big the set of results will be (size). Some error checking is performed, some flags are set to keep track of what is happening and then the sequencer is started (adi_AFE_SeqStart). At this point, the core kicks the sequencer into action and then goes into CORE_SLEEP mode. When both the Rx DMA Done and Sequence Finished interrupts have fired, the core wakes from CORE_SLEEP mode, does some error checking and disables the FIFO and the DMA (adi_AFE_SeqStop). The very last thing the function does before returning is it checks that the CRC and command count elements of the safety word of the sequence array are equal to the CRC and command count values returned by the sequencer (adi_AFE_SeqCheck). 
 Q: How do I determine if I have a CRC error? Is there a flag or error code that I can look at? 
 A: If you are using the adi_AFE_RunSequence function, look at the return code. If it returns ADI_AFE_ERR_SEQ_CHECK, this indicates a CRC error (i.e. a mismatch between the CRC value in the safety word and the value returned by the sequencer to the AFE_SEQ_CRC register) or a command count error (i.e. a mismatch between the command count value in the safety word and the final value in the AFE_SEQ_COUNT register after the sequence has finished). If you step through the function (you will need to set multiple breakpoints to ensure that you &ldquo;run&rdquo; through the piece of code where the sequence is executing, remember, the sequence executes in a separate piece of hardware to the core) you will notice that the last function, adi_AFE_SeqCheck, will return this error. Also remember that if you are setting breakpoints within the adi_AFE_RunSequence function, this is called many times for the power up and calibration steps, before the code ever gets to the actual measurement! 
 Q: I keep getting Command FIFO Underflow interrupts (INT_CMD_FIFO_UDF) when I run my sequence, but I can't see any reason for it. 
 A: The Command FIFO is 8 commands deep. The sequencer will execute 1 MMR write command in a single clock cycle. Once the Command FIFO is no longer full, it will trigger to the DMA that more commands are needed. If the command FIFO is filled with 8 MMR write commands (i.e. if the sequence has 8 consecutive MMR write commands), then these commands will be executed by the sequencer in 8 clock cycles. As soon as the FIFO starts to empty, the DMA gets a request to add more commands. But the DMA cannot fullfill this request in 8 clock cycles, so the sequencer finds an empty Command FIFO and generates an underflow interrupt (INT_CMD_FIFO_UDF). To resolve this, we can delay the sequencer a little to allow the DMA controller to catch up. After (every) 7 consecutive MMR write commands in a sequence, add a short wait (100us should be sufficient). This should resolve the problem. Don't forget to update the command count!!

Question 17

Errata for ADuCM350 I2C serial interface

Accepted Answer

Attached is the errata sheet for the ADuCM350 I2C serial interface

Attachments:

ADuCM350_I2C_errata.pdf

Question 18

ADuCM350 FAQ SPI

Accepted Answer

Q: What is the difference between SPI0/1 and SPIH? 
 A: Each SPI has identical functionality, though SPIH is capable of higher transfer rates. From an SPI programming and users model perspective, SPIH, SPI0, and SPI1 are identical. The main difference between SPIH and SPI0/SPI1 is the internal bus interface that they are connected to. SPIH is connected to a higher performance advanced peripheral bus (APB), which is always clocked at the higher system clock rate (HCLK) and contains fewer modules requiring arbitration. SPI0 and SPI1 are connected to the main advanced peripheral bus (APB), which selectively can be clocked at a lower rate (PCLK) and whose latency is more uncertain due to a greater number of modules requiring arbitration. This means that under higher data rates, SPIH can move data more efficiently and with lower latency. SPIH is recommended for use with high data rate peripherals. 
 Q: Are there any restrictions in programming the SPI in DMA mode? 
 A: All SPI DMA transfers are 16-bit wide and the DMA should be programmed accordingly. For example, if 16 bytes of data are to be transferred over the SPI, the DMA should be programmed to perform eight 16-bit transfers. If 17 bytes are to be transferred, eight 16-bit transfers would be required, the additional byte is discarded. Data errors will occur if the DMA transfers are programmed as byte-wide transfers. This improves DMA efficiency and reduces DMA interrupt overhead. Odd-sized data byte counts in DMA mode cause data buffer overruns.

Q: What is the functionality of TIM bit in the SPI_CONTROL register? 
 A: The TIM bit defines the mode of transfer initiation (in Master mode) and interrupt generation (in master/slave modes). 
 a. It should be set for all cases involving a Tx (either Tx-only or full-duplex). 
 b. For transfers involving Rx only, this bit should be cleared. 
 When TIM=1, SPI starts the transfers with a write to the SPI TX register. 
 When TIM=0, SPI expects a read of Rx-FIFO to start the dta transfer. And most importantly, this read should happen when a byte transmission is not going on. That is, when there is no SCLK toggling happening over the interface. 
 Q: I am using SPI1 to transfer data from the ADuCM350 on the Eval-ADUCM350EBZ. The SCLK doesn't look right and data will only transfer successfully at very low data rates. What is the cause of this? Is it an SPI drive strength problem? 
 A: This is not an SPI drive strength problem. The SPI1 SCLK pin can also be used as an external GPIO. For this reason, a push-button switch (S4) has been implemented on the Eval-ADUCM350EBZ motherboard. This button has an associated de-bounce capacitor (C5) and this cap is affecting the SLI1 SCLK. The solution is to remove 0r resistor R12 from Eval-ADUCM350EBZ, which will isolate the cap and switch.

Q: Is there a minimum high (inactive) time for CS between transfers? 
 
 A: Yes. If CS is to go high (inactive) between transfers, it should be high for a minimum of 1 SCLK period.

Question 19

Unipolar Current Measurement Using ADuCM350

Accepted Answer

ADuCM350 is default configured for bipolar current measurements centered around the TIA bias voltage of 1.1V. 
 The device needs to be configured with a bleed resistor to optimally measure a unipolar current. 
 See attached slideset and adjustements to Switch Mux Config Board for further details.

Attachments:

SwitchMuxConfig0_Unipolar.pdf

UnipolarMeasurementsforAmperometricApplications.pptx

Question 20

Potentiostat / Amperometric Measurement Using ADuCM350

Accepted Answer

System Setup 
 
 Documentation: 
 
 AN-1281 
 
 Hardware 
 
 Eval-ADuCM350EBZ 
 ADuCM350 Switch Mux Config 
 
 Software 
 
 AmperometricMeasurement example in IAR Embedded Workbench 
 
 View data in Comms port

Software Configuration for measuring R5 + R6 (10uF + 6.8 kOhm) 
 Black Text Is Original 
 Red Text is changes from Original 
 
 Validate Results of Setup

Change Switch Matrix so that you measure the 2 kOhm + 6.8 kOhm on ADuCM350 Switch Mux Config Board (AFE 4 to AFE 6). 
 
 Delay after switch mux not required to be significant as switches only see resistors.

Results for measuring 2K + 6.8K 
 
 Results on Serial Comms Terminal 
 Code starts at 32768 (DC Level 1 = 0 V = Midscale) 
 Code Settles at 25790 (DC Level 2 = 300mV)

From Transmit Side: 
 
 Current seen by TIA = ( Step Voltage )/ Z= 300mV/8.8kOhm = 34.09uA 
 2K + 6.8K are 0.1% accurate. 
 
 From Receive Side: 
 
 Input Current Resolution = 3.6V/2^16 1/1.5 1/RTIA = 4.88nA (assumption RTIA=7.5k Ω as on ADuCM350 Switch Mux Board) 
 Code Change in ADC = 32768 – 25790 = 6978 Codes 
 Current seen by TIA = Current Resolution X Code Change in ADC = 4.88nA * 6973 = 34.05uA 
 More accurate series resistors will give better accuracy etc.

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ADuCM350: FAQ