Hi,
I encountered an issue on a SPI communication using MAX32655.
I want to assert a SPI's SS signal ahead of SCK because of an ADC data read communication requirement on AD7176-2.
I disabled the SS0 pin at MXC_SPI_Init() and left the SS0 as GPIO. But my program didn't work.
I found unwanted pulse in the SCK pin as below before starting SPI communication. This happens after assertion of SS0 so this disturbs my SPI communication.
I added OurSet/OutClr function (highlighted red as below) as a flag to find its location and found it happened at the location below in "spi_reva1.c"
MXC_GPIO_OutSet(MXC_GPIO0, MXC_GPIO_PIN_31); // flag
(req->spi)->ctrl0 |= (MXC_F_SPI_REVA_CTRL0_EN);
MXC_GPIO_OutClr(MXC_GPIO0, MXC_GPIO_PIN_31); // flag
In the code, before stating SPI communication, disabling/enabling the SPI HW is required as:
// HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive).
This enablement cause the unwanted pulse. In the capture below, the upper trace is the flag using GPIO toggle, and the lower trace is the unwanted pulse.
I initialized SCK pin (MXC_GPIO_PIN_23) as a GPIO output and set it as 'H' at the beginning, but this didn't affect to the problem.
How can I workaround this?
Please advise.
Regards,
Satoru
