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DMA ready interrupt occurs earlier than real transfer seems to be ready

Category: Hardware
Product Number: ADucm410

I'm using the ADuCM410.

we use the dma controller quite intensively, (adc sampling through scatter gatter, Uart tx and rx and writing to flash memory)

I experienced some issues, with the dma transfer complete interrupt.

If it occurs for a uart tx transition it seems that the last byte of the transfer isn't completely send yet. If I stop the DMA by setting the RMSKSET for the correct dma channel and disabling the channel afterwards in the ENCLR register, immediately when the DMA complete interrupt is executed, I mis the last byte of my transfer. Now I've build in a delay of 2-5ms, but of course I want to get rid of that.

Some for writing to flash. My dma size is configured to 4. If I write a buffer to flash and stop the DMA transfer in a equal way as above at the moment the DMA interrupt occurs, than the last 4 (or perhaps more) bytes aren't written in flash.

Anyone has an idea if this is behavior I have to deal with, if I might have configured something wrong or if someone has a good workaround, let me please know