Category: Datasheet/Specs
Product Number: ADuCM362, ADuCM363
Hello,
In reading over UG1048: ADuCM362/ADuCM363 Hardware Reference Manual, Rev A, I found a discrepancy with the section on the DMA controller. The introduction to the controller mentions and lists 16 channels, but the register map only talks about 12 (12 DMA channel enables, clears, etc). It seems like there's some confusion about whether SPI0 and UART 1 have DMA channels. The introduction to the document and the product description on Analog.com also mention 11 channels (I assume they meant 12?). Can someone confirm that the ADuCM362/3 DMA controller has channels for SPI0 and UART1?
Thanks.
