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SPI DMA sends bytes twice

Thread Summary

The user is experiencing an issue with the ADuCM362 eval board where each byte in the SPI TX buffer is sent twice. The final answer suggests changing the SRC_SIZE and SRC_INC to half word and confirming that DMACHAN_DSC_ALIGN in DmaLib.h is defined as 0x400. The user has provided the buffer declarations and confirmed the byte settings and CCD_SIZE change.
AI Generated Content
Category: Software
Product Number: EVAL-ADUCM362QSPZ

Hi! I am developing a program for the ADuCM362 eval board that utilizes the SPI DMA peripheral in ping-pong mode (only TX). I have been success full in generating SPI writes, however each byte is sent twice. For example the first value in the buffer is decimal 0 and the second is decimal 1. On the oscilloscope I will see "0x00" then "0x00" then the next value "0x01" and then "0x01" again. It doesn't matter what value is being sent nor by which DMA data structure.

I have set DST_SIZE, SRC_SIZE, DST_IN, and SRC_INC all to "byte" or 011. Is there any other SPI or DMA settings that could cause this? I am using the given ADuCM362 drivers and the setup code is shown below.

void SPI1_INIT() {
   SpiFifoFlush(pADI_SPI1, SPICON_TFLUSH_EN, SPICON_RFLUSH_EN);     /* Flush Tx and Rx FIFOs */
   SpiFifoFlush(pADI_SPI1, SPICON_TFLUSH_DIS, SPICON_RFLUSH_EN);     /* Flush Tx and Rx FIFOs */

   // Set mode for SPI1 pins
   DioCfgPin(pADI_GP0, PIN0, 1); // SPI1 MISO
   DioCfgPin(pADI_GP0, PIN1, 1); // SPI1 SCLK
   DioCfgPin(pADI_GP0, PIN2, 1); // SPI1 MOSI
   DioCfgPin(pADI_GP0, PIN3, 1); // SPI1 SS (NOTE: not broken out to anything on my board)

   // Set the SPI1 clock rate in master mode to 1MHz. (SPIDIV)
   SpiBaud(pADI_SPI1, 7, SPIDIV_BCRST_DIS);

   SpiCfg(pADI_SPI1, SPICON_MOD_TX1RX1, SPICON_MASEN_EN, SPICON_CON_EN | SPICON_LOOPBACK_DIS |
            SPICON_RXOF_DIS | SPICON_ZEN_DIS | SPICON_TIM_TXWR | SPICON_CPOL_LOW |
         SPICON_CPHA_SAMPLELEADING | SPICON_ENABLE_EN); // Configure SPI1 channel (SPICON)

   // These all act on the DmaStruct
   DmaPeripheralStructSetup(SPI1TX_C, DMA_DSTINC_NO | DMA_SRCINC_BYTE | DMA_SIZE_BYTE); // Setup SPI1 Tx DMA primary structure
   DmaStructPtrOutSetup(SPI1TX_C, SPI1_TX_BUFFER_SIZE, ucSPI1txPrim);
   DmaCycleCntCtrl(SPI1TX_C, SPI1_TX_BUFFER_SIZE, DMA_PING);

   DmaPeripheralStructSetup(SPI1TX_C+ALTERNATE, DMA_DSTINC_NO | DMA_SRCINC_BYTE | DMA_SIZE_BYTE); // Setup SPI1 Tx DMA alternate structure
   DmaStructPtrOutSetup(SPI1TX_C+ALTERNATE, SPI1_TX_BUFFER_SIZE, ucSPI1txAlt);
   DmaCycleCntCtrl(SPI1TX_C+ALTERNATE, SPI1_TX_BUFFER_SIZE, DMA_PING);

   DmaSet(0, DMAENSET_SPI1TX, 0, 0); // Enable DMA (DMAENSET)
   NVIC_EnableIRQ(DMA_SPI1_TX_IRQn);
}

void DMA_INIT() {
   DmaBase();
}