Post Go back to editing

ADuC8xx interrupt latencies ?

I briefly checked the datasheet(s) but haven't really found concrete numbers on the ADuC8xx interrupt latencies.  Specifically ADuC814 @ 16.78 MHz and ADuC841 @ 20 MHz.  How much time (or cycles) need those from the interrupt signal to the first ISR opcode ?

Parents Reply Children
  • For the ADuC814, the machine cycle consists of 12 core clock periods of the selected core operating frequency. While ADuC841 consists of 1 core clock period.

    ADuC814 @ 16.78MHz - single cycle is around 715ns.
    ADuC841 @ 20MHz - single cycle is around 50ns.

    The interrupts flags are detected in the next machine cycle, and the ISR call takes two cycles. A minimum of three machine cycles elapses from the activation of the interrupt to the beginning of the ISR.

    ADuC814, 3 machine cycle - 2.15us.
    ADuC841, 3 machine cycle - 0.15us.

  • Thanks, that helps and definately should be mentioned the in the "INTERRUPT SYSTEM" datasheet chapter.