AD9371 Lane Assignment - Rx/Tx/ORx

 For JESD204B lane rate  must be within the range 614.4Mbps to 6144Mbps.  The lane rate is the serial bitrate for one lane of the JESD204B link.  Calculate the lane rate using Equation 1.(page 18 of UG-992).
                    L= IQ SampleRate×M×16bits×10/8÷LaneRate

The number of FPGA lanes (GTx Transceivers) can be reduced by going for higher lane rates. The physical design and routing should support for higher datarates. So it depends on design and it will vary with Application and products , So we cannot give a generic recommendation.

UG-992 figure 7 gives more details. Rx and Orx/Snrx has separate framers and these are muxed before the serialiser. As long as you meet the JESD requirements with selected sample rate , converters and number of lanes you can use any combination.

Hi,

I would like to disable RX observation path to enable higher RX sampling rate. I noticed the AD9371 transceiver evaluation SW does not allow it. can you elaborate on how it can be done?

thanks

What is the RX sampling rate that you are looking for ?  The minimum  Rx sampling rate supported by AD9371 is 20 MSPS and maximum is  200MSPS

Rx supports only 100MHz Bandwidth. Observation receive supports 250MHz bandwidth and hence a higher sampling rate is supported in Observation receive path.

Hi Vinod, 

160Msps, single RX path.

It seems the evaluation SW cannot provide all configurations supported by the part and instead of generating the setting using the GUI I need to edit the file generated by the GUI, JESD and headless.c files.

Am I correct in my observation?

thanks

To generate custom data rates use matlab profile generator tool

MATLAB Profile Generator for AD9371 [Analog Devices Wiki]  

You can generate seeings for custom profile by importing the profile as shown below

I did exactly that. Once custom profile is loaded the GUI version 2.0.68 does not generate the C files properly. 

Can you share the generated C file ? 

I managed to reach the ARM calibration stage in the initialization and the SW gets stuck in the following procedure:

if ((mykError = MYKONOS_waitInitCals(&mykDevice, 60000, &errorFlag, &errorCode)) != MYKONOS_ERR_OK) {
errorString = getMykonosErrorMessage(mykError);
goto error;
}

the log upto this point is:

Please wait...
RX_XCVR initialization OK
TX_XCVR initialization OK
RX_OS_XCVR initialization OK
MCS successful
CLKPLL locked
AD9371 ARM version 5.1.1
PLLs locked

what is the reason for getting stuck ?

thanks

Can you disable QEC_init cal and try?

by disabling the TX_QEC and few AGC related checks I managed to pass initialization.

I am now tackling the transceivers: it seems that the RX/RXOS clkgen clocks originating at the transceiver using the CPLL are completely random. The TX clkgen clock generated using the QPLL seems to be fine.

Any clue ?