ad9361_dig_tune: Tuning FAILED! When using no-OS Drivers

I used  no-OS Drivers on the "ZC706 and FMCOMMS3" platform, and designed as a transmitter and reveiver of LTE20M, I just changed default_init_param some elements blow:

{983040000,491520000,245760000,122880000,61440000,30720000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

{983040000,245760000,245760000,122880000,61440000,30720000},//uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

and change filters as blow, which was given by ad9361 Filter Wizard in matlab

AD9361_RXFIRConfig rx_fir_config = {
3, // rx
-6, // rx_gain
2, // rx_dec
{-9,-23,-20,-22,12,20,29,-5,-30,-43,-6,40,64,24,-47,-90,-49,49,122,85,-44,-158,-134,29,196,196,-1,-234,-274,-46,270,368,114,-298,-481,-212,315,612,344,-312,-762,-522,282,935,757,-212,-1133,-1074,80,1365,1510,149,-1646,-2146,-551,2016,3173,1310,-2634,-5298,-3194,4431,14435,21470,21470,14435,4431,-3194,-5298,-2634,1310,3173,2016,-551,-2146,-1646,149,1510,1365,80,-1074,-1133,-212,757,935,282,-522,-762,-312,344,612,315,-212,-481,-298,114,368,270,-46,-274,-234,-1,196,196,29,-134,-158,-44,85,122,49,-49,-90,-47,24,64,40,-6,-43,-30,-5,29,20,12,-22,-20,-23,-9}, // rx_coef[128]
128, // rx_coef_size
{983040000,491520000,245760000,122880000,61440000,30720000}, // rx_path_clks[6]
19365514 // rx_bandwidth
};

AD9361_TXFIRConfig tx_fir_config = {
3, //
0, // tx_gain
2, // tx_int
{-5,0,4,23,36,39,18,-13,-36,-26,11,48,46,-2,-60,-72,-16,69,104,43,-74,-142,-82,71,184,136,-57,-228,-205,26,272,291,25,-311,-395,-101,342,519,210,-357,-663,-361,349,829,564,-307,-1022,-841,216,1251,1225,-44,-1536,-1793,-268,1930,2728,873,-2622,-4718,-2416,4788,13982,20380,20380,13982,4788,-2416,-4718,-2622,873,2728,1930,-268,-1793,-1536,-44,1225,1251,216,-841,-1022,-307,564,829,349,-361,-663,-357,210,519,342,-101,-395,-311,25,291,272,26,-205,-228,-57,136,184,71,-82,-142,-74,43,104,69,-16,-72,-60,-2,46,48,11,-26,-36,-13,18,39,36,23,4,0,-5}, // tx_coef[128]
128, // tx_coef_size
{983040000,245760000,245760000,122880000,61440000,30720000}, // tx_path_clks[6]
19365438 // tx_bandwidth
};

then, I also changed some code in ad9361_api.c, as blow:

phy->bypass_tx_fir = false;
phy->bypass_rx_fir = false;

and all others is the same as the original, but when I run it, it shows then mistakes:

SAMPL CLK: 30720000 tuning: RX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #

ad9361_dig_tune: Tuning RX FAILED!
SAMPL CLK: 30720000 tuning: TX
0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #

ad9361_dig_tune: Tuning TX FAILED!
ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit
ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit
ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit
ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit
ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit
ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit

please help me, there must some thing I did wrong.