The function ad9361_bbpll_set_rate() updates the BBPLL "N" registers as follows:
ad9361_spi_write(spi, REG_INTEGER_BB_FREQ_WORD, integer);
ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_3, fract);
ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_2, fract >> 8);
ad9361_spi_write(spi, REG_FRACT_BB_FREQ_WORD_1, fract >> 16);
The addresses of the registers are defined in ad9361.h:
| #define REG_FRACT_BB_FREQ_WORD_1 | 0x041 /* Fractional BB Freq Word 1 */ | |
| #define REG_FRACT_BB_FREQ_WORD_2 | 0x042 /* Fractional BB Freq Word 2 */ | |
| #define REG_FRACT_BB_FREQ_WORD_3 | 0x043 /* Fractional BB Freq Word 3 */ | |
| #define REG_INTEGER_BB_FREQ_WORD | 0x044 /* Integer BB Freq Word */ |
Yet in the function ad9361_bbpll_recalc_rate() that reads these registers we see:
| ad9361_spi_readm(clk_priv->spi, REG_INTEGER_BB_FREQ_WORD, &buf[0], | |
| REG_INTEGER_BB_FREQ_WORD - REG_FRACT_BB_FREQ_WORD_1 + 1); |
fract = (buf[3] << 16) | (buf[2] << 8) | buf[1];
integer = buf[0];
If I understand ad9361_spi_readm() correctly
that would fill buf[0] with the contents of REG_INTEGER_BB_FREQ_WORD as required,
but buf[1] would be filled with the contents of the register at 0x45, REG_CLOCK_CTRL
buf[2] would be filled with the contents of the register at 0x46, REG_CP_CURRENT
& buf[3] would be filled with the contents of the register at 0x47, REG_CP_BLEED_CURRENT
I presume what we want is
| ad9361_spi_readm(clk_priv->spi, REG_FRACT_BB_FREQ_WORD_1, &buf[0], | |
| REG_INTEGER_BB_FREQ_WORD - REG_FRACT_BB_FREQ_WORD_1 + 1); |
fract = (buf[0] << 16) | (buf[1] << 8) | buf[2];
integer = buf[3];
