KCC's Quizzes AQQ304 - A pure logic
1. Quote of the month: "I am not lazy, I'm just in energy-saving mode" - unknown
2. Quiz AQQ304 about finding a pure logic puzzle
Mike is looking at Anne, but Anne is looking at Paul.
Mike is married, but Paul is not.
Question:
Is a married
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August Monthly Blog Quiz! Read the blog, take the quiz, and you could win a gift card
Important: Read the blog first . The quiz questions are all based on the content of the blog:
Stay in the loop and win! Read the blog Current Output Driving Industrial Loops , then take our quick five-question quiz for a chance to win a gift card
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ADRV9029
Recommended for New Designs
The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation...
Datasheet
ADRV9029 on Analog.com
Dear teams,
When I run the noorx version of dma_example.c in noos/project/adrv902x, the TX data captured with XSCT is 0. could you give me some advice?
boad: zcu102 + adrv9029
hdl main latest HEAD:5ead6f1a9fb88390efbf91c8ce97a888731af856
noos main latest HEAD: 37118746bcd3ce9a42ca11377773777898c28bb4
The serial port output is:
Opened with baud rate: 115200
Zynq MP First Stage Boot Loader
Release 2025.1 May 28 2026 - 06:04:32
PMU-FW is not running, certain applications may not be supported.
adrv9025-phy Rev 0, API version: 7.0.0.14 found
adrv9025-phy Rev 0, API version: 7.0.0.14 found
rx_clkgen: MMCM-PLL locked (245760000 Hz)
tx_clkgen: MMCM-PLL locked (245760000 Hz)
tx_adxcvr: OK (9830400 kHz)
rx_adxcvr: OK (9830400 kHz)
adrv9025-phy Rev 176, Firmware 7.0.0.11 API version: 7.0.0.14 Stream version: 9.4.0.1 successfully initialized via jesd204-fsm
tx_jesd status:
Link is enabled
Measured Link Clock: 245.761 MHz
Reported Link Clock: 245.760 MHz
Lane rate: 9830.400 MHz
Lane rate / 40: 245.760 MHz
LMFC rate: 7.680 MHz
SYNC~: deasserted
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
rx_jesd status:
Link is enabled
Measured Link Clock: 245.761 MHz
Reported Link Clock: 245.760 MHz
Lane rate: 9830.400 MHz
Lane rate / 40: 245.760 MHz
LMFC rate: 7.680 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
DMA_EXAMPLE Tx: address=0x8001e4f00 samples=8192 channels=8 bits=16
DMA_EXAMPLE Rx: address=0x8001ecf00 samples=65536 channels=4 bits=16
tx xsct cmd:xsct ../../tools/scripts/platform/xilinx/capture.tcl ZYNQ_PSU 0x8001e4f00 8192 8 16
rx xsct cmd:xsct ../../tools/scripts/platform/xilinx/capture.tcl ZYNQ_PSU 0x8001ecf00 65536 4 16
best regards,
zhangjinyu
Ramarao - Moved from Support ADRV9022/ADRV9026/ADRV9029 to FPGA Reference Designs. Post date updated from Thursday, May 28, 2026 6:47 AM UTC to Friday, May 29, 2026 9:04 AM UTC to reflect the move.
eserban - Moved from FPGA Reference Designs to Microcontroller no-OS Drivers. Post date updated from Friday, May 29, 2026 9:04 AM UTC to Tuesday, June 2, 2026 9:57 AM UTC to reflect the move.
Hello,
Are there any updates regarding this issue?
All the best,
Eric
Hello,
Are there any updates regarding this issue?
All the best,
Eric