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when run the noorx version of `dma_example.c` in `noos/project/adrv902x`, the TX RX data captured with XSCT is 0.

Thread Summary

The user encountered zero values when capturing TX and RX data with XSCT on a ZCU102 + ADRV9029 setup. The issue was due to 36-bit addresses being truncated to 32 bits in the xsct capture commands. The correct commands should use the truncated addresses (0x001e4f00 for TX and 0x001ecf00 for RX). Additionally, the user reported a hardware issue on board #1, which failed to reset the device and set SPI configuration, while board #2 worked fine with the same code. The user will check the power supply and hardware connections on board #1.
AI Generated Content
Category: Hardware
Product Number: adrv9029

Dear teams,

When I run the noorx version of dma_example.c in noos/project/adrv902x, the TX data captured with XSCT is 0. could you give me some advice?

boad: zcu102 + adrv9029

hdl main latest HEAD:5ead6f1a9fb88390efbf91c8ce97a888731af856

noos main latest HEAD: 37118746bcd3ce9a42ca11377773777898c28bb4

The serial port output is: 

Opened with baud rate: 115200
Zynq MP First Stage Boot Loader 
Release 2025.1   May 28 2026  -  06:04:32
PMU-FW is not running, certain applications may not be supported.
adrv9025-phy Rev 0, API version: 7.0.0.14 found
adrv9025-phy Rev 0, API version: 7.0.0.14 found
rx_clkgen: MMCM-PLL locked (245760000 Hz)
tx_clkgen: MMCM-PLL locked (245760000 Hz)
tx_adxcvr: OK (9830400 kHz)
rx_adxcvr: OK (9830400 kHz)
adrv9025-phy Rev 176, Firmware 7.0.0.11 API version: 7.0.0.14 Stream version: 9.4.0.1 successfully initialized via jesd204-fsm
tx_jesd status:
        Link is enabled
        Measured Link Clock: 245.761 MHz
        Reported Link Clock: 245.760 MHz
        Lane rate: 9830.400 MHz
        Lane rate / 40: 245.760 MHz
        LMFC rate: 7.680 MHz
        SYNC~: deasserted
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_jesd status:
        Link is enabled
        Measured Link Clock: 245.761 MHz
        Reported Link Clock: 245.760 MHz
        Lane rate: 9830.400 MHz
        Lane rate / 40: 245.760 MHz
        LMFC rate: 7.680 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
DMA_EXAMPLE Tx: address=0x8001e4f00 samples=8192 channels=8 bits=16
DMA_EXAMPLE Rx: address=0x8001ecf00 samples=65536 channels=4 bits=16

tx xsct cmd:xsct ../../tools/scripts/platform/xilinx/capture.tcl ZYNQ_PSU 0x8001e4f00 8192 8 16

rx xsct cmd:xsct ../../tools/scripts/platform/xilinx/capture.tcl ZYNQ_PSU 0x8001ecf00 65536 4 16

best regards,

zhangjinyu

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[edited by: JTHY at 9:08 AM (GMT -4) on 28 May 2026]

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