ADRV9371 + ZCU102 bare metal

Hello!

AnshuRaj said:

1. How to get 12 bit of ADC data as in block design i am seeing 1 bit of 4 Rx channels , i am is to perform DSP on received 12 bits of ADC data, please help me for the same 

At the moment it’s not very clear what you are trying to achieve.

Could you please describe your use case in more detail - especially the JESD configuration you intend to use - and attach a screenshot of the block design section where you see those ‘1 bit of 4 RX channels’?

Regards,

Elena

Hi AnshuRaj !

Do you need further assistance?

Regards,

Elena

Hi,

My goal is to perform DSP  on ADC data channels , as we have 12 bit of ADC so, i am looking for to get continue 12 bit of ADC data, Please guide me or suggest correct ways, my doubts are 

1. By HDL repo provides on GIT , by using how to extract 12 bits of ADC data from particular channel.

2. by using the No OS Git repo of ADI , to configure and control the JESD . SPI, is there any modification required in the PS side code or we can use as it is ,Can i use  this  https://github.com/analogdevicesinc/no-OS/tree/main/projects/ad9371  as it is fort zcu102 PS side control and configuration of ADC data,?

as while running the no os git repo i am getting few errors like 

" Use of undeclared identifier 'ADIHAL_LOG_MESSAGE'clang(undeclared_var_use)

"

Please correct me here or guide me to achieve my goal.

yes, Please guide me to get continue data from ADC to perform DSP . using ADI HDL repo and No OS repo from PS side configuration and control

Hi!

Which HDL release are you using (2023_R2 or 2023_R2_p1) and with which no-OS version?

Also, do the errors appear when using the release as-is, or have you made any changes?

Regards,
Elena

Hi , I am using 2023_r2,  https://github.com/analogdevicesinc/hdl/releases/   and in one of the vivado file i modify the version to run on vivado 2024.2, HDl build is successful and bin, xsa  generated , and for no os using this    https://github.com/analogdevicesinc/no-OS/tree/main/projects/ad9371

Hi!

Could you please try to build:

• this HDL project as-is (with no modifications, including no Vivado version changes):  hdl_2023_r2/projects/adrv9371x/zcu102 
• and its corresponding no-OS project: 2023_R2/projects/ad9371 ?

After building them, please let us know whether you still encounter any errors.

Regards,

Elena

yes i did the same , but now 

while buildimg , it is showing--     build successful but in header.c it is showing 21 syntax error, --------------------------------------------------------------------------------

Hello!

If the build completes successfully, please run: make run.

Then open a UART terminal and share with us the log messages.

This will help us better understand the issue.

Regards,

Elena