Hi,
My setup is FMCOMMS3 + ZCU104.
For HDL, I started from the FMCOMMS3 + ZCU102 and modified the HDL to suit ZCU104.
For software, I am using no OS of AD9361 and I am using the DMA example. Again, I have modified the no OS to suit ZCU104. The default example works fine.
I would like to implement a waveform and run the baseband signal processing of the Tx and Rx at 1.28Msamples/s. The default sampling rate in the example I am using is 30.72 MSamples/s so I need to change it to 1.28MSamples/s.
I have been reading different Analog Devices docs and discussions in the forms about related topics. Here is the list of steps that I think I need to do. Could you please have a look at them and let me know if they are right or I am missing something? Thank you!
Step 1- I used the Filter Wizard to configure the sampling rates and the filters of the Tx and Rx chains. Please, find attached the a screen shot of the filter wizard.
Q1/ According to this configuration, I assume that the ADC/DAC runs at 61.44MSamples/s, right?
Q2/ I assume that the baseband logic runs at 1.28MSamples/s, right?
Step 2/
I have exported the coefficients and configs to no-OS and got the followings:
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AD9361_RXFIRConfig rx_fir_config = {
3, // rx
-12, // rx_gain
4, // rx_dec
{100,-44,170,-17,122,-49,-17,-184,-204,-324,-308,-320,-212,-121,34,129,209,187,121,-24,-160,-284,-316,-269,-118,74,273,393,408,281,55,-224,-454,-569,-505,-273,83,448,714,773,586,177,-340,-815,-1080,-1024,-614,62,822,1426,1650,1350,531,-642,-1853,-2713,-2845,-1994,-102,2651,5867,9007,11503,12884,12884,11503,9007,5867,2651,-102,-1994,-2845,-2713,-1853,-642,531,1350,1650,1426,822,62,-614,-1024,-1080,-815,-340,177,586,773,714,448,83,-273,-505,-569,-454,-224,55,281,408,393,273,74,-118,-269,-316,-284,-160,-24,121,187,209,129,34,-121,-212,-320,-308,-324,-204,-184,-17,-49,122,-17,170,-44,100}, // rx_coef[128]
128, // rx_coef_size
{983040000,61440000,20480000,10240000,5120000,1280000}, // rx_path_clks[6]
1068442 // rx_bandwidth
};
AD9361_TXFIRConfig tx_fir_config = {
3, // tx
0, // tx_gain
4, // tx_int
{27,-27,20,-62,-63,-158,-201,-290,-324,-355,-317,-253,-131,-5,128,212,246,201,101,-42,-176,-270,-283,-212,-63,117,281,369,350,215,-3,-245,-433,-503,-416,-186,133,445,650,666,467,89,-367,-762,-958,-865,-471,138,795,1292,1439,1126,369,-672,-1717,-2423,-2468,-1639,102,2588,5463,8254,10464,11685,11685,10464,8254,5463,2588,102,-1639,-2468,-2423,-1717,-672,369,1126,1439,1292,795,138,-471,-865,-958,-762,-367,89,467,666,650,445,133,-186,-416,-503,-433,-245,-3,215,350,369,281,117,-63,-212,-283,-270,-176,-42,101,201,246,212,128,-5,-131,-253,-317,-355,-324,-290,-201,-158,-63,-62,20,-27,27}, // tx_coef[128]
128, // tx_coef_size
{983040000,61440000,20480000,10240000,5120000,1280000}, // tx_path_clks[6]
1255167 // tx_bandwidth
};
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Q3/ I assume that I can use the above exported configs and coeffs to update "default_init_param" in main.c., right?
Q4/ In the exported coeffs and configs above, nothing covers updating the analog filter cut freq. According to the filter wizard GUI, the Fcutoff (analog) is 0.85391 MHz. Do I need to update it? How? Should I use "ad9361_seet_tx_rf_bandwidth" function call?
Q5/ Do I need to update anything in the HDL design in order to run the new sampling rate? Or it is going to be updated by the software changes I am making according to the steps above?
Q6/ In the HDL design, what is the new l_clk frequency?
