Category: Software
Product Number: AD9695
Software Version: Vivado 2022.2
Greetings Sir,
We are presently working on AD9695 with ZCU102, we are in testing stage, we have build vivado part from HDL repos available, and as you suggested we have used AD9208 no-os files for implementing Baremetel for AD9695 both using Xilinx2022_2 using JESD204b.
There is a little issue we are facing while receiving data, let me take you step by step what we have done,
1) There are only two settings we made while configuring HDL before generating bitstream: ADC input clock is 1GHz so lanerate is set to 10Gbps. Setting Converter resolution (N) to 16 itself which was default (should we change it to 14 as the dev is 14-bit ADC or according to datasheet it said to set the default value 16 because once the data comes out from DDC it will be 16-bit resolution itself even if it is full bandwidth the MSB 2bits will be zeros it said) and remaining are set to default {L=4, M=2, N=16, Np=16, S=1, Link=8B10B}.
2) In User-guide "https://wiki.analog.com/resources/eval/user-guides/ad9695_fmc" it was said that the output 64bit of adc_data_0 & adc_data_1 from rx_tpl_core IP are two samples coming at speed of lanerate/40 (250MHz), So I have split them using FIFO where to capture I am using rd_clk = 500MHz (250x2) converting 64bit data into 2x32bit data where considering LSB-16bit as I_data & MSB-16bit as Q_data, and connected it to ILA for debug purpose.
3) No-os was build from AD9028 reference, where that no-os is made for 2-of AD9028 channels, taking it as reference I have changed the required configuration for setting it to 1-Channel, Few parameters and register setting are also changed according to AD9695 requirement (Changes like: frequency min and max setting, clock min and max setting, DDC & decimation settings inside API; few register setting were also changed comparing with AD9695 RegMapping).
4) Jesd parameter setting made: {F=1, K=32, HD=false, N=16, Np=16, M=2, CS=0, L=4, S=1} Inside HDL Octets per Beat is set to 4, but According to the equation JESD follows "M x S x Np = L x F x 8" as samples S required are "1" F was set to "1".
5) more No-os settings: lane_clk = 10G, ref_rate/dev_clk = 250M, decimation=2, carrier_freq = 250MHz, SYSREF mode DISABLED. main.c file is also attached here.
These are the settings and changes made for running and debugging AD9695 with ZCU102.
Connection: On AD9695_EVK the 1GHz clock is connected to P202 & 250MHz ref_clock is connected to J202. A Input data of 100MHz is connected to Analog Input A. Now, while running the application (No issues were faced in both Vitis & Vivado), we are able to observe that some data is being received and it can be seen on ILA, when both ADC_In & FPGA_ref clocks are ON then only the data is being received and when even any one of the clocks is OFF the data is not being received.
Problem: Now the problem we are facing is, while we are trying to verify the data on ILA, it is not showing perfectly, where instead of sine wave we are receiving noise. To debug that again we have placed FFT IP but the output is showing noise only.
Could please suggest a reason why the data is not being received, and could you also suggest how to get the data perfectly.
Edit Notes
Added main.c file of no-os[edited by: TeamDGTL at 4:06 AM (GMT -5) on 12 Dec 2025]
