Post Go back to editing

Cannot reset ADRV9029 DPD when enable DPD Tracking Calibration

Thread Summary

The user encountered an error (Error number 3, Recovery action -2) while trying to enable DPD tracking calibration on ADRV9029 using the no-OS branch R2023_2. The issue is related to the adi_adrv9025_DpdReset function, and the current no-OS branch does not support DPD. The recommended solution is to use the main branch of no-OS, which includes the necessary updates and ORx data path support. The user should ensure the ORx data path is enabled in the HDL and use the latest API version for DPD configuration.
AI Generated Content
Category: Software
Product Number: ADRV9029
Software Version: R2023_2

Hello,

After bring up the ADRV9029 on our custom board, now we need to enable the DPD tracking calibration. I followed the DPD Tracking Calibration Bring Up Sequence (UG1727) but stuck at the adi_adrv9025_DpdReset function.

The log is: ERROR: Error number 3, Recovery action -2. In file ../src/noos/drivers/rf-transceiver/madura/devices/adrv9025/public/src/adi_adrv9025_dfe.c, in function adi_adrv9025_DpdReset, in line 279, variable name cmdStatusByte. Error message CpuCmdStatusWait() failed due to thrown CPU error. CPU time out .

For more information:

  1. I'm using no-OS branch R2023_2
  2. Device information: Silicon Rev : 0xb0; Product ID : 0x84
  3. ADRV9029 is successfully initialized with no-OS APIs. The log is:
    adrv9025-phy Rev 0, API version: 6.4.0.14 found
    tx_adxcvr: OK (9830400 kHz)
    rx_adxcvr: OK (9830400 kHz)
    adrv9025-phy Rev 176, Firmware 6.4.0.6 API version: 6.4.0.14 Stream version: 9.4.0.1 successfully initialized via jesd204-fsm
    tx_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.761 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	LMFC rate: 7.680 MHz
    	SYNC~: deasserted
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
    rx_jesd status:
    	Link is enabled
    	Measured Link Clock: 245.761 MHz
    	Reported Link Clock: 245.760 MHz
    	Lane rate: 9830.400 MHz
    	Lane rate / 40: 245.760 MHz
    	LMFC rate: 7.680 MHz
    	Link status: DATA
    	SYSREF captured: Yes
    	SYSREF alignment error: No
  4. I used Ramarao's code as a reference to enable DPD
  5. The adi_adrv9025_DpdModelConfigSet function returns OK. I used adi_adrv9025_DpdModelConfigGet and the read back model is the same, except txChannelMask = 0x00
  6. I tested with CFR APIs and I think it's working fine. The CFR status is:
    CFR Parameters Readback:
    Tx Channel Mask:1 
    cfrMode:0 
    cfrTxDelay: 511
    cfrPeakThreshold:0.490000 
    cfrEngine1PeakThresholdScaler:0.980000 
    cfrEngine2PeakThresholdScaler:0.985000 
    cfrEngine3PeakThresholdScaler:0.990000 
    cfrCorrectionThresholdScaler:0.980000 
    cfrInterpolationFactor:2 
    cfrEngine1MaxNumOfPeaks:5 
    cfrEngine2MaxNumOfPeaks:5 
    cfrEngine3MaxNumOfPeaks:5
    
    CFR Status Readback:
    CFR_Error_Code:0 
    cfr Engine1 Peaks Detected:0 
    cfr Engine1 Peaks Skipped: 0
    cfr Engine2 Peaks Detected: 2
    cfr Engine2 Peaks Skipped: 0
    cfr Engine3 Peaks Detected: 2
    cfr Engine3 Peaks Skipped: 0
    cfr NumSamples Clipped: 1
    
    CFR Enable Read: 
    tx Channel Mask:1 
    cfr Engine1 Enable:1 
    cfr Engine1 Bypass Enable:0 
    cfr Engine2 Enable:1 
    cfr Engine2 Bypass Enable:0  
    cfr Engine3 Enable:1 
    cfr Engine3 Bypass Enable :0
    *** CFR Configured success***
  7. All other DPD APIs called after adi_adrv9025_DpdReset are failed with Error number 3, Recovery action -2

Is there anything else I need to do to enable DPD?

Parents Reply Children
No Data