Hi all,
We have ad9082 eval board available with us and we need to test it with our FPGA(VCU118) board.
Software tools and version used: Vivado[2022.2], Vitis[2022.2]
As a part of ad9082 evaluation board bringup, we have cloned hdl 2022_r2 and no-OS build from the adi github.
We are building the hdl & no-OS build on our Linux server and connecting remotely to the FPGA board using hw_server.
".xsa" file created after successful build of HDL 2022_r2, is copied to the ad9081 folder of no-OS project cloned from ADI github.
After building no-OS project successfully, 'build' folder which has '.elf' is created without any error.
we have successfully loaded "ad9081.elf" on our FPGA board and also opened Vitis using "sdkopen" command.
We have connected to the target(FPGA) remotely in the Vitis sdk using hw_server.
After building the project file generated in Vitis, when we run the program, We are observing the "Link2 status failed (CGS)" on terminal.
Also, when connected to iioscope, we are observing only axi_adc and axi_dac devices only.
Kindly help us in resolving this issue.
Thanks,
Srikanth.