Category: Software
Product Number: AD9467
Hi,
I recently got the AD9467 250 MHz Evaluation Board and have successfully built the HDL (hdl_2019_r2) from GitHub for the ZedBoard. I also built the No-OS software (2019_R2) for the board without any issues. I am following the instructions from the wiki for bringing up the board. I have not made any modifications (no components were added or removed), and the board is running with default settings.
Here’s my setup:
- I am using the project with its default configuration.
- I provide a 250 MHz clock at the J201 connector with +15dBm power.
- I input a 1 MHz signal at the J100 SMA connector with -20dBm power for the ADC to sample.
I am facing two issues:
- In the ILA core on the FPGA, I only see 12 samples per cycle of the 1 MHz signal, which suggests a sampling frequency of 12 MHz. However, I expect to see 250 samples per cycle.
Can you help clarify why this is happening?
Pl let me know if I am doing something wrong.
Spell Correction
[edited by: imBilal at 5:31 AM (GMT -4) on 16 Oct 2024]
