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					    btoure
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Oct 8, 2024 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
    
		      		            		        
    Category: Software
    
    		        		            		    
    Product Number:  AD9209  
    
    		        		        		        
    Software Version: NO-OS Software
    
    		    		    
    
		    		    
		    			
    
			    
    Hi All,

    Background: 

    

    We've been, for some time now, trying to integrate the ad9081 NO-OS reference design with a AD9209 custom ADC platform with the following target FPGA: Iwave ZU19 (xczu19eg-ffvc1760-1-i).
    


     Our approach was to first use the ZCU102 development board with the ad9081 to ensure that we were able to use the design ok, which we were successful in doing. 
     The second step was to use the ad9081 with the ZU19 but we faced some hardware issues with our ad9081 and thus jumped directly to step3 to integrate the ZU19 with our custom ad9209.

     Key difference between our custom board and the ad9081 MXFE board from ADI is that we are using a RENESAS  8V19N882 as a clock generator instead of the HMC7044.
    

     
    

    The changes made to the design are as follows:

     HDL:
    

      

    • Retargeted the fpga design to use the ZU19 part instead of the ZCU102
      • 

    • Changed the constraints file to remove lines related to the TX and matched the pinout of our board
      • 

    

     
    

    SW:
    

      

    • Disabled TX by assigning variable tx->disable to true in the main file(app.c).
      • 

    • Commented out the setup function in the hmc7044 driver(hmc7044.c) to prevent it from attempting to program the RENESAS clock generator.
      • 

    • Wrote driver for the RENESAS to produce same clock frequencies as the HMC7044
      • 

    • Reduced lane clk frequency from 10G to 3G due to VCO range limit for speed grade 1 device (ZU19) which is different from the ZCU102 speed grade(2).
      • 

    • Changed the logical lane mapping in software to match that of our schematic.
      • 

    

     
    

    Current problem:
    

    The issue being faced right now is that we're able to see data coming out from the Transport Layer when probing the adc data lines with ILA but nothing is displaying on iio-oscilloscope despite the device being detected properly. Note that Im using iio-oscilloscope through windows, but the same thing happens when I decide to use through linux (via WSL). But with linux, everytime i try to cature, the message "Unable to create Buffer" is displayed on the terminal.

    Terminal Printout
    

    

    

    PMIC:   LD01 (BANK 67,68) set to 1.800V
PMIC:   LD04 (BANK 88,89,90,91) set to 1.800V
CLK:    Clk synthesizer-1 configured
CLK:    Clk synthesizer-2 configured
Xilinx Zynq MP First Stage Boot Loader
Release 2022.2   Oct  5 2024  -  04:47:46
PMU-FW is not running, certain applications may not be supported.
Hello
Starting program: )
ADC GPIO control through GPIO
We're in not tx_enable
We're done with not tx_enable
We're done clk_rate_set
DEBUG: adxcvr_clk_set_rate: Rate 3000000 Hz Parent Rate 500000 Hz
DEBUG: xilinx_xcvr_drp_write: drp_port: 256, reg 0x0028, val 0x010a.
DEBUG: xilinx_xcvr_drp_write: drp_port: 256, reg 0x002a, val 0x008c.
DEBUG: xilinx_xcvr_drp_write: drp_port: 256, reg 0x0063, val 0x80c1.
DEBUG: xilinx_xcvr_drp_write: drp_port: 256, reg 0x006d, val 0x349b.
DEBUG: xilinx_xcvr_drp_write: drp_port: 257, reg 0x0028, val 0x010a.
DEBUG: xilinx_xcvr_drp_write: drp_port: 257, reg 0x002a, val 0x008c.
DEBUG: xilinx_xcvr_drp_write: drp_port: 257, reg 0x0063, val 0x80c1.
DEBUG: xilinx_xcvr_drp_write: drp_port: 257, reg 0x006d, val 0x349b.
DEBUG: xilinx_xcvr_drp_write: drp_port: 258, reg 0x0028, val 0x010a.
DEBUG: xilinx_xcvr_drp_write: drp_port: 258, reg 0x002a, val 0x008c.
DEBUG: xilinx_xcvr_drp_write: drp_port: 258, reg 0x0063, val 0x80c1.
DEBUG: xilinx_xcvr_drp_write: drp_port: 258, reg 0x006d, val 0x349b.
DEBUG: xilinx_xcvr_drp_write: drp_port: 259, reg 0x0028, val 0x010a.
DEBUG: xilinx_xcvr_drp_write: drp_port: 259, reg 0x002a, val 0x008c.
DEBUG: xilinx_xcvr_drp_write: drp_port: 259, reg 0x0063, val 0x80c1.
DEBUG: xilinx_xcvr_drp_write: drp_port: 259, reg 0x006d, val 0x349b.
We're done with clk rate set and ret is : 0
AD9081 Rev. 3 Grade 10 (API 1.5.0) probed
tx_dac: Status errors
main:347
rx_adc: Successfully initialized (243533325 Hz)
DEBUG: ad9081_jesd204_link_init:1212 link_num 2 reason initialization
DEBUG: ad9081_jesd204_link_init:1212 link_num 0 reason initialization
DEBUG: hmc7044_jesd204_link_supported:1138 link_num 2 reason initialization
DEBUG: hmc7044_lmfc_lemc_validate: dividend=3000000000 divisor=3906250 GCD=3906250 (hmc->pll2_freq=3000000000, min=732780)DEBUG: hmc7044_jesd204_link_supported:1163 link_num 2 LMFC/LEMC 3906250/3906250 gcd 3906250
DEBUG: hmc7044_jesd204_link_supported:1138 link_num 0 reason initialization
ERR: ../noos/jesd204/jesd204-core.c:144:jesd204_link_validate_params(): link[0], number of lanes is zero
DEBUG: hmc7044_jesd204_link_pre_setup:1367 link_num 2
DEBUG: hmc7044_jesd204_link_pre_setup:1384 Found SYSREF channel3 setting f=3906250 Hz
DEBUG: hmc7044_jesd204_link_pre_setup:1384 Found SYSREF channel13 setting f=3906250 Hz
WARNING: hmc7044_jesd204_link_pre_setup: Link2 forcing continuous SYSREF mode
DEBUG: axi_jesd204_rx_jesd204_link_pre_setup:641 link_num 2 reason initialization
DEBUG: axi_jesd204_rx_jesd204_link_pre_setup: Link2 device clock rate 125000000 (0)
DEBUG: axi_jesd204_rx_jesd204_link_pre_setup: Link2 lane rate 5000000 (0)
DEBUG: axi_jesd204_rx_jesd204_link_pre_setup: Link2 set device clock rate 125000000 Hz
DEBUG: axi_jesd204_rx_jesd204_link_pre_setup: Link2 set link clock rate 125000000 Hz
DEBUG: axi_jesd204_rx_jesd204_link_pre_setup: Link2 set lane rate 5000000 kHz
DEBUG: adxcvr_clk_set_rate: Rate 5000000 Hz Parent Rate 500000 Hz
DEBUG: xilinx_xcvr_drp_write: drp_port: 256, reg 0x0028, val 0x108a.
DEBUG: xilinx_xcvr_drp_write: drp_port: 256, reg 0x002a, val 0x808c.
DEBUG: xilinx_xcvr_drp_write: drp_port: 256, reg 0x0063, val 0x80c0.
DEBUG: xilinx_xcvr_drp_write: drp_port: 256, reg 0x006d, val 0x349b.
DEBUG: xilinx_xcvr_drp_write: drp_port: 257, reg 0x0028, val 0x108a.
DEBUG: xilinx_xcvr_drp_write: drp_port: 257, reg 0x002a, val 0x808c.
DEBUG: xilinx_xcvr_drp_write: drp_port: 257, reg 0x0063, val 0x80c0.
DEBUG: xilinx_xcvr_drp_write: drp_port: 257, reg 0x006d, val 0x349b.
DEBUG: xilinx_xcvr_drp_write: drp_port: 258, reg 0x0028, val 0x108a.
DEBUG: xilinx_xcvr_drp_write: drp_port: 258, reg 0x002a, val 0x808c.
DEBUG: xilinx_xcvr_drp_write: drp_port: 258, reg 0x0063, val 0x80c0.
DEBUG: xilinx_xcvr_drp_write: drp_port: 258, reg 0x006d, val 0x349b.
DEBUG: xilinx_xcvr_drp_write: drp_port: 259, reg 0x0028, val 0x108a.
DEBUG: xilinx_xcvr_drp_write: drp_port: 259, reg 0x002a, val 0x808c.
DEBUG: xilinx_xcvr_drp_write: drp_port: 259, reg 0x0063, val 0x80c0.
DEBUG: xilinx_xcvr_drp_write: drp_port: 259, reg 0x006d, val 0x349b.
DEBUG: axi_jesd204_rx_jesd204_link_pre_setup: Link2 set lane rate 5000000 kHz
DEBUG: hmc7044_jesd204_link_pre_setup:1367 link_num 0
DEBUG: hmc7044_jesd204_link_pre_setup:1384 Found SYSREF channel3 setting f=3906250 Hz
DEBUG: hmc7044_jesd204_link_pre_setup:1384 Found SYSREF channel13 setting f=3906250 Hz
DEBUG: axi_jesd204_tx_jesd204_link_pre_setup:550 link_num 0 reason initialization
ERR: ../noos/jesd204/jesd204-core.c:144:jesd204_link_validate_params(): link[0], number of lanes is zero
DEBUG: axi_jesd204_tx_jesd204_link_pre_setup: Link0 device clock rate 3906250 (-22)
ERR: ../noos/drivers/axi_core/jesd204/axi_jesd204_tx.c:557:axi_jesd204_tx_jesd204_link_pre_setup(): axi_jesd204_tx_jesd204_link_pre_setup: Link0 get device clock rate failed (-22)
DEBUG: axi_jesd204_rx_jesd204_link_setup:697 link_num 2 reason initialization
DEBUG: axi_jesd204_tx_jesd204_link_setup:611 link_num 0 reason initialization
DEBUG: Possible instantiation for multiple chips; HDL lanes 4, Link[0] lanes 0
ERR: ../noos/drivers/axi_core/jesd204/axi_jesd204_tx.c:627:axi_jesd204_tx_jesd204_link_setup(): axi_jesd204_tx_jesd204_link_setup: Link0 enable lane clock failed (-22)
DEBUG: ad9081_jesd204_setup_stage1:1273 reason initialization
DEBUG: ad9081_jesd204_setup_stage2:1338 reason initialization
DEBUG: hmc7044_jesd204_sysref:1078
DEBUG: ad9081_jesd204_setup_stage3:1360 reason initialization
DEBUG: axi_jesd204_rx_jesd204_clks_enable:719 link_num 2 reason initialization
DEBUG: ad9081_jesd204_clks_enable:1058 link_num 2 reason initialization
DEBUG: axi_jesd204_tx_jesd204_clks_enable:642 link_num 0 reason initialization
DEBUG: ad9081_jesd204_clks_enable:1058 link_num 0 reason initialization
DEBUG: axi_jesd204_rx_jesd204_link_enable:741 link_num 2 reason initialization
DEBUG: adxcvr_clk_enable: RX
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
DEBUG: adxcvr_reset: CPLL RX Reset
rx_adxcvr: OK (5000000 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:513:adxcvr_clk_enable(): adxcvr_clk_enable: CPLL RX buffer underflow error, status: 0x61
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:520:adxcvr_clk_enable(): adxcvr_clk_enable: CPLL RX buffer overflow error, status: 0x61
DEBUG: ad9081_jesd204_link_enable:1124 link_num 2 reason initialization
DEBUG: hmc7044_jesd204_sysref:1078
DEBUG: axi_jesd204_tx_jesd204_link_enable:663 link_num 0 reason initialization
DEBUG: ad9081_jesd204_link_enable:1124 link_num 0 reason initialization
DEBUG: hmc7044_jesd204_sysref:1078
DEBUG: axi_jesd204_rx_jesd204_link_running:789 link_num 2 reason initialization
DEBUG: ad9081_jesd204_link_running:1147 link_num 2 reason initialization
JESD RX (JTX) Link2 in DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid
DEBUG: axi_jesd204_tx_jesd204_link_running:686 link_num 0 reason initialization
ERR: ../noos/drivers/axi_core/jesd204/axi_jesd204_tx.c:697:axi_jesd204_tx_jesd204_link_running(): axi_jesd204_tx_jesd204_link_running: Link0 status failed (CGS)
DEBUG: ad9081_jesd204_link_running:1147 link_num 0 reason initialization
tx_jesd status:
        Link is enabled
        Measured Link Clock: 243.530 MHz
        Reported Link Clock: 250.000 MHz
        Lane rate: 3000.000 MHz
        Lane rate / 40: 75.000 MHz
        LMFC rate: 1.171 MHz
        SYNC~: asserted
        Link status: CGS
        SYSREF captured: disabled
        SYSREF alignment error: disabled
rx_jesd status:
        Link is enabled
        Measured Link Clock: 243.530 MHz
        Reported Link Clock: 250.000 MHz
        Lane rate: 3000.000 MHz
        Lane rate / 40: 75.000 MHz
        LMFC rate: 2.343 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
       
        Running IIOD server...
        If successful, you may connect an IIO client application by:
        1. Disconnecting the serial terminal you use to view this message.
        2. Connecting the IIO client application using the serial backend configured as shown:
        Baudrate: 115200
        Data size: 8 bits
        Parity: none
        Stop bits: 1
        Flow control: none


    

    

    ILA Capture

     
    

    

    IIO Oscilloscope
    

     
    

     
    

     
    

    

    Is there anyone that can assist with this? 

    Regards.
    

    
			
    
			
									
		                                 
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                 Clock Generation Devices
                
                                                    
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                 iio-oscilloscope
                
                                        
                                            
                
                
                                        
                                            
                
                
                                        
                                            
                
                
                                        
                                            
                
                
                                        
                                            
                
                
                                        
                                            
                
                
                                        
                                            
                
                
                                        
                                            
                
                
                                
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