Modify a AD4134 non-OS environment driver to a Linux kernel driver for operation on the NXP i.MX8

Hello,

Here are a couple of links which should help to clear up at least some of the questions on the FPGA side

https://analogdevicesinc.github.io/hdl/projects/ad4134_fmc/index.html

https://analogdevicesinc.github.io/hdl/library/spi_engine/index.html

The SPI Engine is basically a SPI controller with certain features tailored for interfacing with ADI precision converters. The point of the SPI Engine is to facilitate data transfer at the highest rates possible while trying to meet the device's timing constraints. The AD4134 has a classic SPI interface used for register access and a separate custom SPI/parallel interface for ADC sample data. The SPI engine is used to interface with the latter. As you can see in the project documentation, there is also a PWM core involved which will trigger the SPI Engine transfers with one channel and drive the ODR signal with a second channel. There are certain timing requirements that are solved using this solution. The purpose of ODR and the timing relations with the other signals are all explained in the datasheet.

I assume you could use something different than the SPI Engine to read data from the AD4134 but you will probably do it at a (much) lower data rate. It very much depends on how capable the system is since it is not only a question of SPI clock speed but you also need a way to drive ODR correctly while meeting the timing requirements.

~Sergiu

Hi sarpadi ,

Thank you for your guidance.

I’m currently facing a similar situation and would appreciate it if you could clarify a couple of points:

1. You mentioned, "you will probably do it at a (much) lower data rate." Could you elaborate on what you mean by this? Specifically, how much reduction in the Output Data Rate (ODR) should we expect in such a scenario?

2. Additionally, if we configure the AD4134 in ASRC Master Mode (Datasheet Page no: 39), where the device manages both the ODR and DCLK signals, does this imply that we no longer need to be concerned with manually controlling the ODR signal?

Please correct me if I’m mistaken.

Thank you again for your assistance!

Hello,

In this context I am referring to the FPGA support using the SPI Engine with the part in Slave mode so excluding that design, I can only estimate.

Using the chip in Master mode means that it will generate ODR but it will also generate the DCLK so you will need a SPI Controller that supports input SCLK. I believe the ADC can format data and send it on only one data line.

If you can manage to use a standard SPI controller (Zynq PS SPI or equivalent) to read sample data, using ORD as interrupt, in this mode you can probably expect sample rates in the range of ~10/20 ksps. This would be my guess.

~Sergiu