AD9082 + ZC706??

Hi D-Tech ,

ZC706 has GTX transceivers that are limited  to lane rate of 10.3125 Gbps. The FMC connector has 8 GTX lanes, so L can be 8

What profile do you plan using?

Regards,

George

I need 2000-2500 (Not variable, just the sampling range I need for the system) Gsps IQ into and out of 1 ADC/DAC JESD channel.

Can the ZC706 + AD9082-FMCA-EBZ support @ 10 GHz DAC/5GHz ADC this JESD mode??

Tx Mode:
JESD Mode Number 18 txBW 2000.0 Total Int 4 Coarse Int 2 Fine Int 2 Dual Link False JESD Deframer JESD204C L 8 M 2 F 1 S 2 K 256 N 16 NP 16 LaneRate 10.3125
Rx Mode:
JESD Mode Number 19.00 rxBW 2035.0 Total Dec 2 Coarse Dec 2 Fine Dec 1 Dual Link False JESD Framer JESD204C Async False L 8 M 2 F 1 S 2 K 256 NP 16 LaneRate 10.3125

The ACE tool calculates a Tx/Rx Ref Clock of 156.25 MHz. Is this the FPGA PL clock? refclk with 4 ns constraint in the hdl project?

My license for the 7045 on the ZC706 is maxed out at 2021.1 for Vivado so I can't upgrade any further.

Hello,

We do not have support for JESD204C in ZC706 devices. Will a JESD204B work for your case ?

Regards,

Adrian

Is JESD204C supported in the ad9082_fmca_ebz_zcu102 hdl project? 

Also, I only see reference to the 9081 in the no-OS, can it also support the 9082?  

Hi D-Tech ,

"Is JESD204C supported in the ad9082_fmca_ebz_zcu102 hdl project? "

No, as the following line specifies:

github.com/.../system_project.tcl

"Also, I only see reference to the 9081 in the no-OS, can it also support the 9082?  "

no-OS can support AD9082 (in situations when their capabilities overlap):

github.com/.../ad9081.c

Regards,

George

I don't think so.

When I try and get the sampling rate using JESDB with the mode selector script and then plug that into the ACE software I get ref clocks that are ~500 MHz. If I am right in assuming this is the FPGA PL clock, it would be really hard if not impossible to get it to pass timing. Using JESD204C gives me ~125MHz ref clock rates. 

Was it removed at some point? Or only supported in Linux? This guy seems to be using C.

 https://ez.analog.com/sw-interface-tools/f/q-a/563931/ad9081-unable-to-get-jesd204c-adc-mode-27-0-dac-mode-20-working 

Is there a hardware restriction on the zcu102 board? Or is it a Xilinx license thing for the JESD204C? This vpk180 project seems to support JESD204C:

https://github.com/analogdevicesinc/hdl/blob/fc3d48f930e3b502f11804c2e586809e127dc62e/projects/ad9082_fmca_ebz/vpk180/system_project.tcl#L38

In other words, exactly what hardware and licenses' do I need to purchase for supporting JESD204C modes 18 and 19 above with no-OS.

Hello,

The JESD204C limitation is related to the transceivers in the Zynq 7 Series FPGA. We do not have support for them for the 64/66b mode. 

In ZCU102 we have support for JESD204, up to a lane rate of 16Gbps. 

You need a Xilinx license for Vivado that typically comes with ZCU102.

For the JESD204 IP, when going to production you need to purchase a license from ADI or have the project licensed under GPL2 (hdl/LICENSE_ADIJESD204 at main · analogdevicesinc/hdl (github.com))

Regards,

Adrian

So, I can run JESD204C 64B/66B mode on the zcu102 as long I keep the lane rate below 16Gbps? 

Yes ZCU102 functions with JESD204C. The Linux devicetrees show examples of different modes and usually contain the HDL make settings used. Here is an example: https://github.com/analogdevicesinc/linux/blob/6babf6ef103420eb19db1cf9159e76f245fc1bc0/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-204c-txmode0-rxmode1.dts#L25

-Travis

Are there app_config.h files that correspond to the linux dts files? Most of it is self explanatory but I am having trouble understanding the RX_LOGICAL_LANE_MAPPING and RX_LINK_CONVERTER_SELECT defines.

I tried matching my app_config.h and app_clock.c with this dts

https://github.com/analogdevicesinc/linux/blob/6babf6ef103420eb19db1cf9159e76f245fc1bc0/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9082-204c-txmode22-rxmode23.dts

/***************************************************************************//**
 *   @file   app_config.h
 *   @brief  Application configuration.
 *   @author DBogdan (dragos.bogdan@analog.com)
********************************************************************************
 * Copyright 2020(c) Analog Devices, Inc.
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *  - Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  - Neither the name of Analog Devices, Inc. nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *  - The use of this software may or may not infringe the patent rights
 *    of one or more patent holders.  This license does not release you
 *    from the requirement that you obtain separate licenses from these
 *    patent holders to use this software.
 *  - Use of the software either in source or binary form, must be run
 *    on or directly connected to an Analog Devices Inc. component.
 *
 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef APP_CONFIG_H_
#define APP_CONFIG_H_

#ifdef QUAD_MXFE
#define MULTIDEVICE_INSTANCE_COUNT	4
#else
#define MULTIDEVICE_INSTANCE_COUNT	1
#endif

#define AD9081_DAC_FREQUENCY	11520000000
#define AD9081_ADC_FREQUENCY	3840000000
#ifdef QUAD_MXFE
#define AD9081_ADC_NYQUIST_ZONE	{1, 1, 1, 1}
#else
#define AD9081_ADC_NYQUIST_ZONE	{0, 0, 0, 0}
#endif

/* TX path */

#define AD9081_TX_JESD_MODE		22
#define AD9081_TX_JESD_SUBCLASS		0
#define AD9081_TX_JESD_VERSION		2
#define AD9081_TX_JESD_M		2
#define AD9081_TX_JESD_F		3
#define AD9081_TX_JESD_K		256
#define AD9081_TX_JESD_N		12
#define AD9081_TX_JESD_NP		12
#define AD9081_TX_JESD_CS		0
#define AD9081_TX_JESD_L		2
#define AD9081_TX_JESD_S		2
#define AD9081_TX_JESD_HD		0
#ifdef QUAD_MXFE
#define AD9081_TX_LOGICAL_LANE_MAPPING	{0, 1, 2, 3, 4, 5, 6, 7}
#else
#define AD9081_TX_LOGICAL_LANE_MAPPING	{0, 2, 7, 7, 1, 7, 7, 3}
#endif

#define AD9081_JRX_TPL_PHASE_ADJUST 0x0c //Not found in dts

#define AD9081_TX_MAIN_INTERPOLATION	12
#define AD9081_TX_CHAN_INTERPOLATION	1
#define AD9081_TX_MAIN_NCO_SHIFT	{1000000000, 1100000000, 1200000000, 1300000000}
#define AD9081_TX_CHAN_NCO_SHIFT	{0, 0, 0, 0, 0, 0, 0, 0}
#define AD9081_TX_CHAN_GAIN		{2048, 2048, 2048, 2048, 0, 0, 0, 0}

#define AD9081_TX_DAC_CHAN_CROSSBAR	{0x1, 0x2, 0x4, 0x8} //Not found in dts

/* RX path */

#define AD9081_RX_JESD_MODE		23
#define AD9081_RX_JESD_SUBCLASS		0
#define AD9081_RX_JESD_VERSION		2
#define AD9081_RX_JESD_M		2
#define AD9081_RX_JESD_F		6
#define AD9081_RX_JESD_K		128
#define AD9081_RX_JESD_N		12
#define AD9081_RX_JESD_NP		12
#define AD9081_RX_JESD_CS		0
#define AD9081_RX_JESD_L		2
#define AD9081_RX_JESD_S		4
#define AD9081_RX_JESD_HD		0
#ifdef QUAD_MXFE
#define AD9081_RX_LOGICAL_LANE_MAPPING	{0, 1, 2, 3, 4, 5, 6, 7} 
#else
#define AD9081_RX_LOGICAL_LANE_MAPPING	{2, 0, 7, 7, 7, 7, 3, 1}
#endif
#define AD9081_RX_LINK_CONVERTER_SELECT	{0, 1, 2, 3, 8, 9, 10, 11, 0, 0, 0, 0, 0, 0, 0, 0} //Not found in dts

#define AD9081_RX_MAIN_DECIMATION	{4, 4, 0, 0}
#define AD9081_RX_CHAN_DECIMATION	{1, 1, 0, 0, 0, 0, 0, 0}
#define AD9081_RX_MAIN_ENABLE		{1, 1, 0, 0}
#define AD9081_RX_CHAN_ENABLE		{1, 1, 0, 0, 0, 0, 0, 0}
#define AD9081_RX_MAIN_NCO_SHIFT	{400000000, -400000000, 100000000, 100000000}
#define AD9081_RX_CHAN_NCO_SHIFT	{0, 0, 0, 0, 0, 0, 0, 0}

#endif

/***************************************************************************//**
 *   @file   app_clock.c
 *   @brief  Application clocks initialization.
 *   @author DBogdan (dragos.bogdan@analog.com)
********************************************************************************
 * Copyright 2020(c) Analog Devices, Inc.
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *  - Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  - Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  - Neither the name of Analog Devices, Inc. nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *  - The use of this software may or may not infringe the patent rights
 *    of one or more patent holders.  This license does not release you
 *    from the requirement that you obtain separate licenses from these
 *    patent holders to use this software.
 *  - Use of the software either in source or binary form, must be run
 *    on or directly connected to an Analog Devices Inc. component.
 *
 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/

/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include "no_os_spi.h"
#include "xilinx_spi.h"
#include "hmc7044.h"
#ifdef QUAD_MXFE
#include "adf4371.h"
#include "no_os_gpio.h"
#include "xilinx_gpio.h"
#endif
#include "no_os_error.h"
#include "parameters.h"
#include "app_clock.h"

/******************************************************************************/
/************************ Variables Definitions *******************************/
/******************************************************************************/
struct hmc7044_dev* hmc7044_dev;

struct no_os_clk_hw hmc7044_hw;

#ifdef QUAD_MXFE
struct adf4371_dev* adf4371_dev[MULTIDEVICE_INSTANCE_COUNT];

struct no_os_clk_hw adf4371_hw[MULTIDEVICE_INSTANCE_COUNT];
#endif

/******************************************************************************/
/************************** Functions Implementation **************************/
/******************************************************************************/
/**
 * @brief Application clock setup.
 * @return 0 in case of success, -1 otherwise.
 */
int32_t app_clock_init(struct no_os_clk dev_refclk[MULTIDEVICE_INSTANCE_COUNT])
{
	int32_t ret;

	struct xil_spi_init_param xil_spi_param = {
#ifdef PLATFORM_MB
		.type = SPI_PL,
#else
		.type = SPI_PS,
#endif
	};

	struct no_os_spi_init_param clkchip_spi_init_param = {
#ifdef QUAD_MXFE
		.device_id = SPI_2_DEVICE_ID,
#else
		.device_id = CLK_SPI_DEVICE_ID,
#endif
		.max_speed_hz = 10000000,
		.mode = NO_OS_SPI_MODE_0,
#ifdef QUAD_MXFE
		.chip_select = HMC7043_CS,
#else
		.chip_select = CLK_CS,
#endif
		.platform_ops = &xil_spi_ops,
		.extra = &xil_spi_param
	};

#ifdef QUAD_MXFE
	struct hmc7044_chan_spec chan_spec[] = {
		{
			.num = 0,				// FPGA_REFCLK
			.divider = 1,				// 500 MHz
			.driver_mode = 2,			// LVDS
		}, {
			.num = 1,				// SYSREF_MXFE0
			.divider = 256,				// 1.953125 MHz
			.driver_mode = 2,			// LVDS
			.start_up_mode_dynamic_enable = true,
			.high_performance_mode_dis = true,
			.coarse_delay = 0,
			.fine_delay = 24,
			.out_mux_mode = 1,
		}, {
			.num = 3,				// SYSREF_MXFE1
			.divider = 256,				// 1.953125 MHz
			.driver_mode = 2,			// LVDS
			.start_up_mode_dynamic_enable = true,
			.high_performance_mode_dis = true,
			.coarse_delay = 1,
			.fine_delay = 0,
			.out_mux_mode = 0,
		}, {
			.num = 5,				// SYSREF_MXFE2
			.divider = 256,				// 1.953125 MHz
			.driver_mode = 2,			// LVDS
			.start_up_mode_dynamic_enable = true,
			.high_performance_mode_dis = true,
			.coarse_delay = 0,
			.fine_delay = 16,
			.out_mux_mode = 1,
		}, {
			.num = 7,				// SYSREF_MXFE3
			.divider = 256,				// 1.953125 MHz
			.driver_mode = 2,			// LVDS
			.start_up_mode_dynamic_enable = true,
			.high_performance_mode_dis = true,
			.coarse_delay = 0,
			.fine_delay = 0,
			.out_mux_mode = 0,
		}, {
			.num = 8,				// CORE_LINK_CLK
			.divider = 2,				// 250 MHz
			.driver_mode = 2,			// LVDS
		}, {
			.num = 9,				// SYSREF_FPGA
			.divider = 256,				// 1.953125 MHz
			.driver_mode = 2,			// LVDS
			.start_up_mode_dynamic_enable = true,
			.high_performance_mode_dis = true,
			.coarse_delay = 0,
			.fine_delay = 0,
			.out_mux_mode = 0,
		}
	};

	struct hmc7044_init_param hmc7044_param = {
		.spi_init = &clkchip_spi_init_param,
		.is_hmc7043 = true,
		.clkin_freq = {500000000, 0, 0, 0},
		.sysref_timer_div = 1024,
		.pulse_gen_mode = 7,
		.rf_reseeder_disable = true,
		.in_buf_mode = {0x07, 0x07, 0x00, 0x00, 0x00},
		.gpi_ctrl = {0x00, 0x00, 0x00, 0x00},
		.gpo_ctrl = {0x37, 0x00, 0x00, 0x00},
		.num_channels = sizeof(chan_spec) /
		sizeof(struct hmc7044_chan_spec),
		.channels = chan_spec
	};

	struct xil_gpio_init_param xil_gpio_param = {
#ifdef PLATFORM_MB
		.type = GPIO_PL,
#else
		.type = GPIO_PS,
#endif
		.device_id = GPIO_DEVICE_ID
	};
	struct no_os_gpio_init_param gpio_adrf5020_ctrl = {
		.number = ADRF5020_CTRL_GPIO,
		.platform_ops = &xil_gpio_ops,
		.extra = &xil_gpio_param
	};
	no_os_gpio_desc *adrf5020_ctrl;
	int32_t i;

	ret = no_os_gpio_get(&adrf5020_ctrl, &gpio_adrf5020_ctrl);
	if (ret)
		return ret;

	ret = no_os_gpio_set_value(adrf5020_ctrl, 1);
	if (ret)
		return ret;

#else
#if defined(PLATFORM_ZYNQMP)
	struct hmc7044_chan_spec chan_spec[] = {
		{
			.num = 0,		// CORE_CLK_RX
			.divider = 48,		// 250 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 2,		// DEV_REFCLK
			.divider = 4,		// 250 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 3,		// DEV_SYSREF
			.divider = 768,	// 1.953125 MHz
			.driver_mode = 2,	// LVDS
			//.is_sysref = true,
			.disable = true,
		}, {
			.num = 6,		// CORE_CLK_TX
			.divider = 24,		// 250 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 8,		// CORE_CLK_RX
			.divider = 64,		// 500 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 10,		// CORE_CLK_RX_ALT
			.divider = 48,		// 250 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 12,		// FPGA_REFCLK
			.divider = 8,		// 500 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 13,		// FPGA_SYSREF
			.divider = 768,	// 1.953125 MHz
			.driver_mode = 2,	// LVDS
			//.is_sysref = true,
			.disable = true,
		}
	};
#elif defined(PLATFORM_MB)
	struct hmc7044_chan_spec chan_spec[] = {
		{
			.num = 0,		// CORE_CLK_RX
			.divider = 12,		// 250 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 2,		// DEV_REFCLK
			.divider = 12,		// 250 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 3,		// DEV_SYSREF
			.divider = 1536,	// 1.953125 MHz
			.driver_mode = 2,	// LVDS
			.is_sysref = true,
		}, {
			.num = 6,		// CORE_CLK_TX
			.divider = 12,		// 250 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 8,		// CORE_CLK_RX_ALT2
			.divider = 12,		// 250 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 10,		// CORE_CLK_RX_ALT
			.divider = 12,		// 250 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 12,		// FPGA_REFCLK2
			.divider = 6,		// 500 MHz
			.driver_mode = 2,	// LVDS
		}, {
			.num = 13,		// FPGA_SYSREF
			.divider = 1536,	// 1.953125 MHz
			.driver_mode = 2,	// LVDS
			.is_sysref = true,
		}
	};
#endif

	struct hmc7044_init_param hmc7044_param = {
		.spi_init = &clkchip_spi_init_param,
		/*
		* There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ:
		* VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
		* VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
		* To determine the version, read the frequency printed on the VCXO.
		*/
		//.clkin_freq = {122880000, 30720000, 0, 0},
		//.vcxo_freq = 122880000,
		.clkin_freq = {100000000, 10000000, 0, 0},
		.vcxo_freq = 100000000,
		.pfd1_limit = 1000000,
		.pll1_cp_current = 720,
		.pll2_freq = 2880000000,
		.pll1_loop_bw = 200,
		.sysref_timer_div = 1024,
		.in_buf_mode = {0x07, 0x07, 0x00, 0x00, 0x15},
		.gpi_ctrl = {0x00, 0x00, 0x00, 0x00},
		.gpo_ctrl = {0x37, 0x33, 0x00, 0x00},
		.num_channels = sizeof(chan_spec) /
		sizeof(struct hmc7044_chan_spec),
		.pll1_ref_prio_ctrl = 0xe4,//not found it dts
		.pll1_ref_autorevert_en = false,//not found it dts
		.sync_pin_mode = 0x1,//not found it dts
		.high_performance_mode_clock_dist_en = false,//not found it dts
		.pulse_gen_mode = 0x0,
		.channels = chan_spec
	};
#endif

	ret = hmc7044_init(&hmc7044_dev, &hmc7044_param);
	if (ret)
		return ret;

#ifdef QUAD_MXFE
	struct adf4371_chan_spec adf_chan_spec[1] = {
		{
			.num = 2,
			.power_up_frequency = 12000000000,
		}
	};

	struct adf4371_init_param adf4371_param = {
		.spi_init = &clkchip_spi_init_param,
		.spi_3wire_enable = true,
		.clkin_frequency = 500000000,
		.muxout_select = 1,
		.num_channels = 1,
		.channels = adf_chan_spec
	};

	for (i = 0; i < MULTIDEVICE_INSTANCE_COUNT; i++) {
		clkchip_spi_init_param.chip_select = ADF4371_CS + i;
		ret = adf4371_init(&adf4371_dev[i], &adf4371_param);
		if (ret)
			return ret;

		adf4371_hw[i].dev = adf4371_dev[i];
		adf4371_hw[i].dev_clk_recalc_rate = adf4371_clk_recalc_rate;
		adf4371_hw[i].dev_clk_round_rate = adf4371_clk_round_rate;
		adf4371_hw[i].dev_clk_set_rate = adf4371_clk_set_rate;

		dev_refclk[i].hw = &adf4371_hw[i];
		dev_refclk[i].hw_ch_num = 2;
		dev_refclk[i].name = "dev_refclk";
	}
#else
	hmc7044_hw.dev = hmc7044_dev;

	dev_refclk[0].hw = &hmc7044_hw;
	dev_refclk[0].hw_ch_num = 2;
	dev_refclk[0].name = "dev_refclk";

	struct no_os_clk_desc *clk_desc;
	struct no_os_clk_init_param clk_desc_init = { 0 };

	clk_desc_init.dev_desc = hmc7044_dev;
	clk_desc_init.hw_ch_num = 2;
	clk_desc_init.name = "dev_refclk";
	clk_desc_init.platform_ops = &hmc7044_clk_ops;

	ret = no_os_clk_init(&clk_desc, &clk_desc_init);
	if (ret)
		return ret;

	dev_refclk[0].clk_desc = clk_desc;

#endif

	return 0;
}

/**
 * @brief Application clocking remove.
 * @return 0 in case of success, -1 otherwise.
 */
int32_t app_clock_remove(void)
{
	return hmc7044_remove(hmc7044_dev);
}

I get this out of the com port:

Xilinx Zynq MP First Stage Boot Loader
Release 2021.1   Oct 17 2024  -  20:56:28
PMU-FW is not running, certain applications may not be supported.
Hello
PLL1: Locked, CLKIN0 @ 100000000 Hz, PFD: 1000 kHz - PLL2: Locked @ 2880.000000 MHz
AD9081 Rev. 3 Grade 2 (API 1.5.0) probed
tx_dac: Successfully initialized (959985351 Hz)
rx_adc: Successfully initialized (480004882 Hz)
WARNING: hmc7044_jesd204_link_pre_setup: Link2 forcing continuous SYSREF mode
ERR: ../noos/drivers/axi_core/jesd204/axi_jesd204_rx.c:675:axi_jesd204_rx_jesd204_link_pre_setup(): axi_jesd204_rx_jesd204_link_pre_setup: Link2 set lane rate 11880000 kHz failed (-22)
ERR: ../noos/drivers/axi_core/jesd204/axi_jesd204_tx.c:582:axi_jesd204_tx_jesd204_link_pre_setup(): axi_jesd204_tx_jesd204_link_pre_setup: Link0 set lane rate 11880000 kHz failed (-22)
tx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
rx_adxcvr: OK (10000000 kHz)
ERR: ../noos/drivers/axi_core/jesd204/axi_adxcvr.c:520:adxcvr_clk_enable(): adxcvr_clk_enable: CPLL RX buffer overflow error, status: 0x41
ERR: ../noos/drivers/axi_core/jesd204/axi_jesd204_rx.c:804:axi_jesd204_rx_jesd204_link_running(): axi_jesd204_rx_jesd204_link_running: Link2 status failed (WAIT_BS)
JESD RX (JTX) Link2 PLL locked, PHASE established, MODE valid
JESD TX (JRX) Link0 204C status: Undef (1)
tx_jesd status:
        Link is enabled
        Measured Link Clock: 89.999 MHz
        Reported Link Clock: 250.000 MHz
        Lane rate: 10000.000 MHz
        Lane rate / 66: 151.515 MHz
        LEMC rate: 4.734 MHz
        Link status: DATA
        SYSREF captured: disabled
        SYSREF alignment error: disabled
rx_jesd status:
        Link is enabled
        Measured Link Clock: 89.999 MHz
        Reported Link Clock: 250.000 MHz
        Lane rate: 10000.000 MHz
        Lane rate / 66: 151.515 MHz
        LEMC rate: 4.734 MHz
        Link status: WAIT_BS
        SYSREF captured: disabled
        SYSREF alignment error: disabled
Running IIOD server...
                      If successful, you may connect an IIO client application by:
                                                                                  1. Disconnecting the serial terminal you use to view this message.
                                                                                                                                                    2. Connecting the IIO client application using the serial backend configured as shown:
                                                Baudrate: 115200
                                                                        Data size: 8 bits
                                                                                                Parity: none
                                                                                                                Stop bits: 1
                                                                                                                                Flow control: none

Hi D-Tech ,

You will also have to compile an xsa from the HDL repository with the exact same settings. You will most probably have to modify also the clock settings since the rates fail to be set:

https://github.com/analogdevicesinc/no-OS/blob/5bb963bd188c0bd35072e8181a33a086b254641e/projects/ad9081/src/app_clock.c#L197

Regards,

George

Hi D-Tech ,

You will also have to compile an xsa from the HDL repository with the exact same settings. You will most probably have to modify also the clock settings since the rates fail to be set:

https://github.com/analogdevicesinc/no-OS/blob/5bb963bd188c0bd35072e8181a33a086b254641e/projects/ad9081/src/app_clock.c#L197

Regards,

George