AD9082 + ZC706??

Hi D-Tech ,

ZC706 has GTX transceivers that are limited  to lane rate of 10.3125 Gbps. The FMC connector has 8 GTX lanes, so L can be 8

What profile do you plan using?

Regards,

George

I need 2000-2500 (Not variable, just the sampling range I need for the system) Gsps IQ into and out of 1 ADC/DAC JESD channel.

Can the ZC706 + AD9082-FMCA-EBZ support @ 10 GHz DAC/5GHz ADC this JESD mode??

Tx Mode:
JESD Mode Number 18 txBW 2000.0 Total Int 4 Coarse Int 2 Fine Int 2 Dual Link False JESD Deframer JESD204C L 8 M 2 F 1 S 2 K 256 N 16 NP 16 LaneRate 10.3125
Rx Mode:
JESD Mode Number 19.00 rxBW 2035.0 Total Dec 2 Coarse Dec 2 Fine Dec 1 Dual Link False JESD Framer JESD204C Async False L 8 M 2 F 1 S 2 K 256 NP 16 LaneRate 10.3125

The ACE tool calculates a Tx/Rx Ref Clock of 156.25 MHz. Is this the FPGA PL clock? refclk with 4 ns constraint in the hdl project?

My license for the 7045 on the ZC706 is maxed out at 2021.1 for Vivado so I can't upgrade any further.

For my future reference I ran the following with the 2021_R1 branch and the project built with no errors...

make RX_RATE=10.3125 TX_RATE=10.3125 RX_JESD_M=2 RX_JESD_8=4 RX_JESD_S=2 RX_JESD_NP=16 TX_JESD_M=2 TX_JESD_L=8 TX_JESD_S=2 TX_JESD_NP=16

no-OS branch 2021_R1 Fails to build in parameters.h line 91

......

#define DDR_CNTRL_BASEADDR XPAR_PSU_DDRC_0_BASEADDR
#define CLK_CS 0
#else
#error Unsupported platform.
#endif

.....

no-OS branch 2021_R1 Fails to build in parameters.h line 91

......

#define DDR_CNTRL_BASEADDR XPAR_PSU_DDRC_0_BASEADDR
#define CLK_CS 0
#else
#error Unsupported platform.
#endif

.....