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AD9082 + ZC706??

Category: Software
Product Number: AD9082

I see HDL support for AD9082 https://github.com/analogdevicesinc/hdl/tree/main/projects/ad9082_fmca_ebz/zc706

I cannot find no-OS specific support but the wiki says it is supported. I only see AD9081 and ZCU102/VCU118 listed in the no-OS project.

If the ZC706 is supported are there JESD204C limitations? The Zynq on the 706 only has GTH transceivers, so are the TX/RX lanes limited to ~15 Gbp/s? Can it only support L = 4 or the full 8? How about the K parameter? I see modes that I would like to use with K = 128/256 but I am unsure what limitations come with this parameter.

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  • Hi  ,

    ZC706 has GTX transceivers that are limited  to lane rate of 10.3125 Gbps. The FMC connector has 8 GTX lanes, so L can be 8

    What profile do you plan using?

    Regards,

    George

  • I need 2000-2500 (Not variable, just the sampling range I need for the system) Gsps IQ into and out of 1 ADC/DAC JESD channel.

    Can the ZC706 + AD9082-FMCA-EBZ support @ 10 GHz DAC/5GHz ADC this JESD mode??

    Tx Mode:
    JESD Mode Number 18 txBW 2000.0 Total Int 4 Coarse Int 2 Fine Int 2 Dual Link False JESD Deframer JESD204C L 8 M 2 F 1 S 2 K 256 N 16 NP 16 LaneRate 10.3125
    Rx Mode:
    JESD Mode Number 19.00 rxBW 2035.0 Total Dec 2 Coarse Dec 2 Fine Dec 1 Dual Link False JESD Framer JESD204C Async False L 8 M 2 F 1 S 2 K 256 NP 16 LaneRate 10.3125

    The ACE tool calculates a Tx/Rx Ref Clock of 156.25 MHz. Is this the FPGA PL clock? refclk with 4 ns constraint in the hdl project?

    My license for the 7045 on the ZC706 is maxed out at 2021.1 for Vivado so I can't upgrade any further.



  • For my future reference I ran the following with the 2021_R1 branch and the project built with no errors...

    make RX_RATE=10.3125 TX_RATE=10.3125 RX_JESD_M=2 RX_JESD_8=4 RX_JESD_S=2 RX_JESD_NP=16 TX_JESD_M=2 TX_JESD_L=8 TX_JESD_S=2 TX_JESD_NP=16

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