AD9082 + ZC706??

Hi D-Tech ,

ZC706 has GTX transceivers that are limited  to lane rate of 10.3125 Gbps. The FMC connector has 8 GTX lanes, so L can be 8

What profile do you plan using?

Regards,

George

Hi D-Tech ,

ZC706 has GTX transceivers that are limited  to lane rate of 10.3125 Gbps. The FMC connector has 8 GTX lanes, so L can be 8

What profile do you plan using?

Regards,

George

I need 2000-2500 (Not variable, just the sampling range I need for the system) Gsps IQ into and out of 1 ADC/DAC JESD channel.

Can the ZC706 + AD9082-FMCA-EBZ support @ 10 GHz DAC/5GHz ADC this JESD mode??

Tx Mode:
JESD Mode Number 18 txBW 2000.0 Total Int 4 Coarse Int 2 Fine Int 2 Dual Link False JESD Deframer JESD204C L 8 M 2 F 1 S 2 K 256 N 16 NP 16 LaneRate 10.3125
Rx Mode:
JESD Mode Number 19.00 rxBW 2035.0 Total Dec 2 Coarse Dec 2 Fine Dec 1 Dual Link False JESD Framer JESD204C Async False L 8 M 2 F 1 S 2 K 256 NP 16 LaneRate 10.3125

The ACE tool calculates a Tx/Rx Ref Clock of 156.25 MHz. Is this the FPGA PL clock? refclk with 4 ns constraint in the hdl project?

My license for the 7045 on the ZC706 is maxed out at 2021.1 for Vivado so I can't upgrade any further.

For my future reference I ran the following with the 2021_R1 branch and the project built with no errors...

make RX_RATE=10.3125 TX_RATE=10.3125 RX_JESD_M=2 RX_JESD_8=4 RX_JESD_S=2 RX_JESD_NP=16 TX_JESD_M=2 TX_JESD_L=8 TX_JESD_S=2 TX_JESD_NP=16

no-OS branch 2021_R1 Fails to build in parameters.h line 91

......

#define DDR_CNTRL_BASEADDR XPAR_PSU_DDRC_0_BASEADDR
#define CLK_CS 0
#else
#error Unsupported platform.
#endif

.....

Hello,

We do not have support for JESD204C in ZC706 devices. Will a JESD204B work for your case ?

Regards,

Adrian

Is JESD204C supported in the ad9082_fmca_ebz_zcu102 hdl project? 

Also, I only see reference to the 9081 in the no-OS, can it also support the 9082?  

Hi D-Tech ,

"Is JESD204C supported in the ad9082_fmca_ebz_zcu102 hdl project? "

No, as the following line specifies:

github.com/.../system_project.tcl

"Also, I only see reference to the 9081 in the no-OS, can it also support the 9082?  "

no-OS can support AD9082 (in situations when their capabilities overlap):

github.com/.../ad9081.c

Regards,

George

I don't think so.

When I try and get the sampling rate using JESDB with the mode selector script and then plug that into the ACE software I get ref clocks that are ~500 MHz. If I am right in assuming this is the FPGA PL clock, it would be really hard if not impossible to get it to pass timing. Using JESD204C gives me ~125MHz ref clock rates. 

Was it removed at some point? Or only supported in Linux? This guy seems to be using C.

 https://ez.analog.com/sw-interface-tools/f/q-a/563931/ad9081-unable-to-get-jesd204c-adc-mode-27-0-dac-mode-20-working 

Is there a hardware restriction on the zcu102 board? Or is it a Xilinx license thing for the JESD204C? This vpk180 project seems to support JESD204C:

https://github.com/analogdevicesinc/hdl/blob/fc3d48f930e3b502f11804c2e586809e127dc62e/projects/ad9082_fmca_ebz/vpk180/system_project.tcl#L38

In other words, exactly what hardware and licenses' do I need to purchase for supporting JESD204C modes 18 and 19 above with no-OS.

Hello,

The JESD204C limitation is related to the transceivers in the Zynq 7 Series FPGA. We do not have support for them for the 64/66b mode. 

In ZCU102 we have support for JESD204, up to a lane rate of 16Gbps. 

You need a Xilinx license for Vivado that typically comes with ZCU102.

For the JESD204 IP, when going to production you need to purchase a license from ADI or have the project licensed under GPL2 (hdl/LICENSE_ADIJESD204 at main · analogdevicesinc/hdl (github.com))

Regards,

Adrian

So, I can run JESD204C 64B/66B mode on the zcu102 as long I keep the lane rate below 16Gbps? 

Yes ZCU102 functions with JESD204C. The Linux devicetrees show examples of different modes and usually contain the HDL make settings used. Here is an example: https://github.com/analogdevicesinc/linux/blob/6babf6ef103420eb19db1cf9159e76f245fc1bc0/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-204c-txmode0-rxmode1.dts#L25

-Travis