In the no os environment, when initializing AD9988, the TX link can be configured normally every time, but sometimes the RX link may print and enter the DATA stage, and sometimes it may get stuck in the CGS and ILAS stages.
What is this related to?
I am using XILINX's IP and comparing two projects. One is the ADI project and the other is the project I built myself. The ADI project always enters the DATA phase correctly, but sometimes the project I built myself may not enter the DATA state.
What are the reasons that may affect me?
thanks a lot!
[locked by: buha at 7:53 AM (GMT -5) on 4 Mar 2025]