I'm using the dac_fmc_ebz_zcu102 vivado project to create the xsa for my no-os build. There is no no-OS AD9164 project, so I had to piece together the drivers from the exisitng AD916x linux files and AD9172 no-OS example. My transceiver lane rate is 15.4 GHz. The MGT clk is 385 MHz. My DAC clk is 6.16 GHz.
This is my output from the terminal.
tx_adxcvr: OK (15400000 kHz)
AD916x DAC Chip ID: 4
AD916x DAC Product ID: 9164
AD916x DAC Product Grade: 0
AD916x DAC Product Revision: 6
AD916x Revision: 1.0.0
ad9162_init : AD916x Rev 1 successfully initialized
tx_jesd status:
Link is enabled
Measured Link Clock: 385.037 MHz
Reported Link Clock: 385.000 MHz
Lane rate: 15400.000 MHz
Lane rate / 40: 385.000 MHz
LMFC rate: 24.062 MHz
SYNC~: deasserted
Link status: WAIT
SYSREF captured: disabled
SYSREF alignment error: disabled
tx_dac: Successfully initialized (3080310058 Hz)
DLL Status: 0
DAC clock DLL is not locked to DAC clock input (0x092 Bit 0)
DLL Status: 0
SERDES PLL is not locked (0x281 Bit 0)
I have several questions:
1. The tx_jesd status says the link is stuck in the WAIT status. This means that the link is not up. My Vitis code sets up the ADF4355 and AD9508 PLL's to provide the MGT clk of 385 MHz. Could the issue be that transceiver is not getting a free-running clock on start-up and before deasserting reset?
2. The tx_dac says it is successfully initialized, but why is the frequency 3.08 GHz instead of 6.16 GHz?
3. The DLL and SERDES PLL status tells me the DAC input clock is not receiving the 6.16 GHz as it should. I was able to confirm 6.16 GHz output coming out of the ADF4355 and the ADCLK914BCPZ via the J62 output port. I confirmed the HMC849A switch was set low to output the PLL clock. Is there any other suggestions on what I should do?
