Post Go back to editing

ADRV9008-2 ORX at 491.42MSPS whit noise and DC

Category: Hardware
Product Number: ADRV9008-2

Hello,

I want to use ADRV9008-2 at 491.52 MSPS for TX and ORX.

I'm working on EVAL-TPG-ZYNQ3 + ADRV9008-2 W/PCBZ boards, with no-OS firmware.

If I look at the data received from ORX input I see some noise and a DC component quite high.

I already looked at "ADRV9008-2: problem with 491.52 MSPS profile" thread, but I see something that is different.

Looking at the spectrum I get without input signal (see figure) I note that at central frequencies the noise is higher than reported in that thread, and above all I have a DC component very high.


This is the configuration file I used (is what comes with no-OS release):

/**
 * \file adrv9009/profiles/tx_bw400_ir491p52_rx_bw200_or245p76_orx_bw400_or491p52_dc245p76/talise_config.c
 * \brief Contains Talise configuration settings for the Talise API
 *
 * Copyright 2015-2017 Analog Devices Inc.
 * Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
 *
 * The top level structure taliseDevice_t talDevice uses keyword
 * extern to allow the application layer main() to have visibility
 * to these settings.
 *
 * This file may not be fully complete for the end user application and
 * may need to updated for AGC, GPIO, and DAC full scale settings.
 * To create a full initialisation routine, the user should also refer to the
 * Iron Python initialisation routine generated by the GUI, and also the Talise User Guide.
 *
 */

#include "talise_types.h"
#include "talise_config.h"
#include "talise_error.h"
#include "talise_agc.h"
#ifdef ADI_ZYNQ_PLATFORM
#include "zynq_platform.h"
#endif

int16_t txFirCoefs[20] = {32, -76, 124, -160, 176, -121, -145, 1031, -3015, 20138, -3015, 1031, -145, -121, 176, -160, 124, -76, 32, 0};

int16_t rxFirCoefs[24] = {-194, -715, 777, 907, -1163, -1890, 2240, 3306, -4068, -7024, 9205, 31112, 31112, 9205, -7024, -4068, 3306, 2240, -1890, -1163, 907, 777, -715, -194};

int16_t obsrxFirCoefs[24] = {-44, 22,-18, -1, 32, -75, 83, -81, -15, 354, -1940, 19672, -1940, 354, -15, -81, 83, -75, 32, -1, -18, 22, -44, 0};

#ifdef ADI_ZYNQ_PLATFORM /** < Insert Customer Platform HAL State Container here>*/
/*
 * Platform Layer SPI settings - this structure is specific to ADI's platform layer code.
 * User should replace with their own structure or settings for their hardware
 */
zynqSpiSettings_t spiDev1 = {
	.chipSelectIndex = 1,
	.writeBitPolarity = 0,
	.longInstructionWord = 1,
	.CPHA = 0,
	.CPOL = 0,
	.mode = 0,
	.spiClkFreq_Hz = 25000000
};

/*
 * Platform Layer settings - this structure is specific to ADI's platform layer code.
 * User should replace with their own structure or settings for their hardware
 * The structure is held in taliseDevice_t below as a void pointer, allowing
 * the customer to pass any information for their specific hardware down to the
 * hardware layer code.
 */
zynqAdiDev_t talDevHalInfo = {
	.devIndex = 1,
	.spiSettings = &spiDev1,
	.spiErrCode = 0,
	.timerErrCode = 0,
	.gpioErrCode = 0,
	.logLevel = ADIHAL_LOG_ALL
};
#endif
/**
 *  TalDevice a structure used by the Talise API to hold the platform hardware
 *  structure information, as well as an internal Talise API state container
 *  (devStateInfo) of runtime information used by the API.
 **/
taliseDevice_t talDevice = {
#ifdef ADI_ZYNQ_PLATFORM
	/* Void pointer of users platform HAL settings to pass to HAL layer calls
	 * Talise API does not use the devHalInfo member */
	.devHalInfo = &talDevHalInfo,
#else
	.devHalInfo = NULL,     /* < Insert Customer Platform HAL State Container here>*/
#endif
	/* devStateInfo is maintained internal to the Talise API, just create the memory */
	.devStateInfo = {0}

};

taliseInit_t talInit = {
	/* SPI settings */
	.spiSettings =
	{
		.MSBFirst            = 1,  /* 1 = MSBFirst, 0 = LSBFirst */
		.enSpiStreaming      = 0,  /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
		.autoIncAddrUp       = 1,  /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
		.fourWireMode        = 1,  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
		.cmosPadDrvStrength  = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
	},

	/* Rx settings */
	.rx =
	{
		.rxProfile =
		{
			.rxFir =
			{
				.gain_dB = -6,                /* filter gain */
				.numFirCoefs = 24,            /* number of coefficients in the FIR filter */
				.coefs = &rxFirCoefs[0]
			},
			.rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
			.rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
			.rhb1Decimation = 1,            /* RX Half band 1 decimation (1 or 2) */
			.rxOutputRate_kHz = 245760,            /* Rx IQ data rate in kHz */
			.rfBandwidth_Hz = 200000000,    /* The Rx RF passband bandwidth for the profile */
			.rxBbf3dBCorner_kHz = 200000,    /* Rx BBF 3dB corner in kHz */
			.rxAdcProfile = {185, 141, 172, 90, 1280, 942, 1332, 90, 1368, 46, 1016, 19, 48, 48, 37, 208, 0, 0, 0, 0, 52, 0, 7, 6, 42, 0, 7, 6, 42, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 31, 905},            /* pointer to custom ADC profile */
			.rxDdcMode = TAL_RXDDC_BYPASS,   /* Rx DDC mode */
			.rxNcoShifterCfg =
			{
				.bandAInputBandWidth_kHz = 0,
				.bandAInputCenterFreq_kHz = 0,
				.bandANco1Freq_kHz = 0,
				.bandANco2Freq_kHz = 0,
				.bandBInputBandWidth_kHz = 0,
				.bandBInputCenterFreq_kHz = 0,
				.bandBNco1Freq_kHz = 0,
				.bandBNco2Freq_kHz = 0
			}
		},
		.framerSel = TAL_FRAMER_A,            /* Rx JESD204b framer configuration */
		.rxGainCtrl =
		{
			.gainMode = TAL_MGC,            /* taliserxGainMode_t gainMode */
			.rx1GainIndex = 255,            /* uint8_t rx1GainIndex */
			.rx2GainIndex = 255,            /* uint8_t rx2GainIndex */
			.rx1MaxGainIndex = 255,            /* uint8_t rx1MaxGainIndex */
			.rx1MinGainIndex = 195,            /* uint8_t rx1MinGainIndex */
			.rx2MaxGainIndex = 255,            /* uint8_t rx2MaxGainIndex */
			.rx2MinGainIndex = 195            /* uint8_t rx2MinGainIndex */
		},
		.rxChannels = TAL_RX1RX2,                /* The desired Rx Channels to enable during initialization */
	},


	/* Tx settings */
	.tx =
	{
		.txProfile =
		{
			.dacDiv = 1,                        /* The divider used to generate the DAC clock */
			.txFir =
			{
				.gain_dB = 0,                        /* filter gain */
				.numFirCoefs = 20,                    /* number of coefficients in the FIR filter */
				.coefs = &txFirCoefs[0]
			},
			.txFirInterpolation = 1,                    /* The Tx digital FIR filter interpolation (1,2,4) */
			.thb1Interpolation = 2,                    /* Tx Halfband1 filter interpolation (1,2) */
			.thb2Interpolation = 2,                    /* Tx Halfband2 filter interpolation (1,2)*/
			.thb3Interpolation = 1,                    /* Tx Halfband3 filter interpolation (1,2)*/
			.txInt5Interpolation = 1,                    /* Tx Int5 filter interpolation (1,5) */
			.txInputRate_kHz = 491520,                    /* Primary Signal BW */
			.primarySigBandwidth_Hz = 150000000,    /* The Rx RF passband bandwidth for the profile */
			.rfBandwidth_Hz = 400000000,            /* The Tx RF passband bandwidth for the profile */
			.txDac3dBCorner_kHz = 400000,                /* The DAC filter 3dB corner in kHz */
			.txBbf3dBCorner_kHz = 200000,                /* The BBF 3dB corner in kHz */
			.loopBackAdcProfile = {186, 148, 176, 90, 1280, 901, 1479, 225, 1401, 85, 995, 21, 48, 48, 36, 207, 0, 0, 0, 0, 52, 0, 0, 6, 24, 0, 0, 6, 24, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 15, 905}
		},
		.deframerSel = TAL_DEFRAMER_A,                    /* Talise JESD204b deframer config for the Tx data path */
		.txChannels = TAL_TX1TX2,                            /* The desired Tx channels to enable during initialization */
		.txAttenStepSize = TAL_TXATTEN_0P05_DB,            /* Tx Attenuation step size */
		.tx1Atten_mdB = 10000,                            /* Initial Tx1 Attenuation */
		.tx2Atten_mdB = 10000,                            /* Initial Tx2 Attenuation */
		.disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO    /* Options to disable the transmit data when the RFPLL unlocks. */
	},


	/* ObsRx settings */
	.obsRx =
	{
		.orxProfile =
		{
			.rxFir =
			{
				.gain_dB = 6,                /* filter gain */
				.numFirCoefs = 24,            /* number of coefficients in the FIR filter */
				.coefs = &obsrxFirCoefs[0]
			},
			.rxFirDecimation = 1,            /* Rx FIR decimation (1,2,4) */
			.rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
			.rhb1Decimation = 1,            /* RX Half band 1 decimation (1 or 2) */
			.orxOutputRate_kHz = 491520,            /* Rx IQ data rate in kHz */
			.rfBandwidth_Hz = 400000000,    /* The Rx RF passband bandwidth for the profile */
			.rxBbf3dBCorner_kHz = 225000,    /* Rx BBF 3dB corner in kHz */
			.orxLowPassAdcProfile = {113, 171, 181, 90, 1280, 1737, 1574, 839, 1305, 297, 846, 74, 30, 41, 32, 193, 0, 0, 0, 0, 48, 0, 0, 0, 24, 0, 0, 0, 24, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 15, 905},
			.orxBandPassAdcProfile = {113, 171, 181, 90, 1280, 1737, 1574, 839, 1305, 297, 846, 74, 30, 41, 32, 193, 0, 0, 0, 0, 48, 0, 0, 0, 24, 0, 0, 0, 24, 0, 25, 27, 0, 0, 25, 27, 0, 0, 165, 44, 15, 905},
			.orxDdcMode = TAL_ORXDDC_DISABLED,   /* ORx DDC mode */
            .orxMergeFilter  = {-167, 419, -208, -498, 968, -320, -1273, 2154, -402, -4155, 9170, 21413}
		},
		.orxGainCtrl =
		{
			.gainMode = TAL_MGC,
			.orx1GainIndex = 255,
			.orx2GainIndex = 255,
			.orx1MaxGainIndex = 255,
			.orx1MinGainIndex = 195,
			.orx2MaxGainIndex = 255,
			.orx2MinGainIndex = 195
		},
		.framerSel = TAL_FRAMER_B,                /* ObsRx JESD204b framer configuration */
		.obsRxChannelsEnable = TAL_ORX1,        /* The desired ObsRx Channels to enable during initialization */
		.obsRxLoSource = TAL_OBSLO_RF_PLL                /* The ORx mixers can use the TX_PLL */
	},

	/* Digital Clock Settings */
	.clocks =
	{
		.deviceClock_kHz = 245760,            /* CLKPLL and device reference clock frequency in kHz */
		.clkPllVcoFreq_kHz = 9830400,        /* CLKPLL VCO frequency in kHz */
		.clkPllHsDiv = TAL_HSDIV_2P5,            /* CLKPLL high speed clock divider */
		.rfPllUseExternalLo = 0,                /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
		.rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC                /* RFPLL MCS (Phase sync) mode */
	},

	/* JESD204B settings */
	.jesd204Settings =
	{
		/* Framer A settings */
		.framerA =
		{
			.bankId = 1,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
			.M = 2,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
			.K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
			.F = 2,                            /* F (number of bytes per frame) */
			.Np = 16,                            /* Np (converter sample resolution) */
			.scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
			.externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
			.serializerLanesEnabled = 0x03,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
			.serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
			.lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbInSelect = 0,                /* syncbInSelect; */
			.overSample = 0,                    /* 1=overSample, 0=bitRepeat */
			.syncbInLvdsMode = 1,
			.syncbInLvdsPnInvert = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Framer B settings */
		.framerB =
		{
			.bankId = 0,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
			.M = 2,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
			.K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
			.F = 2,                            /* F (number of bytes per frame) */
			.Np = 16,                            /* Np (converter sample resolution) */
			.scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
			.externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
			.serializerLanesEnabled = 0x0C,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
			.serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
			.lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbInSelect = 1,                /* syncbInSelect; */
			.overSample = 0,                    /* 1=overSample, 0=bitRepeat */
			.syncbInLvdsMode = 1,
			.syncbInLvdsPnInvert = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Deframer A settings */
		.deframerA =
		{
			.bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
			.M = 4,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
			.K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
			.scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
			.externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
			.deserializerLanesEnabled = 0x0F,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
			.deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
			.lmfcOffset = 17,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbOutSelect = 0,                /* SYNCBOUT0/1 select */
			.Np = 16,                /* Np (converter sample resolution) */
			.syncbOutLvdsMode = 1,
			.syncbOutLvdsPnInvert = 0,
			.syncbOutCmosSlewRate = 0,
			.syncbOutCmosDriveLevel = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		/* Deframer B settings */
		.deframerB =
		{
			.bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
			.deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
			.lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
			.M = 0,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
			.K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
			.scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
			.externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
			.deserializerLanesEnabled = 0x00,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
			.deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
			.lmfcOffset = 0,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
			.newSysrefOnRelink = 0,            /* newSysrefOnRelink */
			.syncbOutSelect = 1,                /* SYNCBOUT0/1 select */
			.Np = 16,                /* Np (converter sample resolution) */
			.syncbOutLvdsMode = 1,
			.syncbOutLvdsPnInvert = 0,
			.syncbOutCmosSlewRate = 0,
			.syncbOutCmosDriveLevel = 0,
			.enableManualLaneXbar = 0 /* 0=auto, 1=manual */
		},
		.serAmplitude = 15,                    /* Serializer amplitude setting. Default = 15. Range is 0..15 */
		.serPreEmphasis = 1,                /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
		.serInvertLanePolarity = 0,            /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
		.desInvertLanePolarity = 0,            /* Deserializer Lane PN inversion select.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
		.desEqSetting = 1,                    /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
		.sysrefLvdsMode = 1,                /* Use LVDS inputs on Talise for SYSREF */
		.sysrefLvdsPnInvert = 0              /*0= Do not PN invert SYSREF */
	}
};

//Only needs to be called if user wants to setup AGC parameters
static taliseAgcCfg_t rxAgcCtrl = {
	4,
	255,
	195,
	255,
	195,
	30720,  /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
	10,
	10,
	16,
	0,
	1,
	0,
	0,
	0,
	1,
	31,
	246,
	4,
	1,          /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
	/* agcPower */
	{
		1,      /*!<1-bit field, enables the Rx power measurement block. */
		1,      /*!<1-bit field, allows using Rx PFIR for power measurement. */
		0,      /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
		9,      /*!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
		2,      /*!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where  max = 0xF, min = 0x00 */
		4,      /*!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step  size, 5-bit register value where max = 0x1F, min = 0x00 */
		4,      /*!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
		5,      /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
		2,      /*!<Default value should be 2*/
		0,
		0
	},
	/* agcPeak */
	{
		205,        /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
		2,          /*!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of  agcUnderRangeLowInterval  , Default: 4 */
		4,          /*!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
		39,         /*!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
		49,         /*!<AGC APD peak detect high threshold. default = 0x1F, 6-bit register value where max = 0x3F, min = 0x00.  Set to 3dB below apdHighThresh */
		23,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
		19,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max = 0x3F, min = 0x00 . Set to 3dB below apdLowThresh  */
		6,          /*!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20  */
		3,          /*!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00  */
		4,          /*!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register  value, where max = 0x1F, min = 0x00  */
		2,          /*!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00  */
		1,          /*!<1-bit field, enables or disables the HB2 overload detector.  */
		1,          /*!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
		1,          /*!<4-bit field. Sets the number of actual overloads required to trigger the overload signal.  */
		181,        /*!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
		45,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		90,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		128,        /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
		6,          /*!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min =  0x20 */
		3,          /*!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
		2,          /*!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
		4,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number  of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
		8,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
		4,          /*!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
		1,
		0,
		0
	}
};

I've seen that also the ORX input chain has a DC correction block that may be bypassed, but I don't know how to activate it.

Thank you

Maurizio



deleted replicated file
[edited by: maurizio.sonzogni@abe.it at 2:42 PM (GMT -5) on 21 Feb 2024]

Thread Notes

Parents
  • can you please share the setup connection that you are using, did you connect the feedback signal to ORx? Please share these details to understand more about the issue.

    Use the below API to enable the ORX DC offset.

  • Thank you RR4,

    I'm using this environment:

    - FPGA project is the adrv9009/zc706 project from hdl repository. I've made a little modification sending data to TX channels from a block memory ROM, and looking for ORX data with an ILA.

    - Software project is the adrv9009 project from no-OS repository, the DMA_EXAMPLE option.

    I generate a single side-band sine waveform on both TX1 and TX2, and the spectrum in the above image is calculated from the captured data in ILA when the ORX1 input is not connected to any signal (the input has a 50 ohm clamp).

    I see the same behavior if I put the TX1 signal on ORX1 (via a 20 dB attenuator): in this case I see the correct signal plus the noise and DC component as in the above figure.

    I've tried to make a call to the suggested API: I've made the call to this API after the call to the TALISE_enableTrackingCals API, and before the calls to the TALISE_radioOn and the TALISE_setRxTxEnable APIs in the talise_setup function, but the result is very strange, as you can see in this picture:

    The signal goes from -32768 to 32767 and sometimes around tho 0 value but with some noise and some DC component.

    Is there something else to do when calling the TALISE_setDigDcOffsetEn API?

    Thank you

    Maurizio

  • Moving to another forum to answer no-Os related questions

  • What versions of TES and no-OS are you using ?

    Also, please describe how exactly you use the TES generated the config files with no-OS.

    I'm pretty sure the HDL on the SD card won't properly work with newer Talise API/no-OS/TES so make sure you use a matching HDL. If your no-OS is main branch, use HDL from main branch. If no-OS is a specific release, use HDL from the matching release.

  • I've recompiled all (both no-OS and HDL projects with actual main branch).

    In no-OS I've selected the profile for 491.52 MSPS to make the project.

    I still see the same problem for DC component and noise.

    In any case the TES version is 3.6.2.1 with:

    FPGA version 4E00021A.

    arm version 6.2.1 build type = TAL_ARM_BUILD_RELEASE

    Stream version 2.17

    The boot log of the board with the SD card is:

    
    U-Boot 2014.01-dirty (Jul 21 2014 - 14:45:35)
    
    I2C:   ready
    Memory: ECC disabled
    DRAM:  1 GiB
    MMC:   zynq_sdhci: 0
    SF: Detected S25FL128S_64K with page size 512 Bytes, erase size 128 KiB, total 32 MiB
    *** Warning - bad CRC, using default environment
    
    In:    serial
    Out:   serial
    Err:   serial
    Net:   Gem.e000b000
    Hit any key to stop autoboot:  0 
    Device: zynq_sdhci
    Manufacturer ID: 3
    OEM: 5344
    Name: SB16G 
    Tran Speed: 50000000
    Rd Block Len: 512
    SD version 3.0
    High Capacity: Yes
    Capacity: 14.8 GiB
    Bus Width: 4-bit
    reading uEnv.txt
    ** Unable to read file uEnv.txt **
    Copying Linux from SD to RAM...
    reading uImage
    2999904 bytes read in 290 ms (9.9 MiB/s)
    reading devicetree.dtb
    11848 bytes read in 14 ms (826.2 KiB/s)
    reading uramdisk.image.gz
    ** Unable to read file uramdisk.image.gz **
    ## Booting kernel from Legacy Image at 03000000 ...
       Image Name:   Linux-3.14.0-g5ea3bc9
       Image Type:   ARM Linux Kernel Image (uncompressed)
       Data Size:    2999840 Bytes = 2.9 MiB
       Load Address: 00008000
       Entry Point:  00008000
       Verifying Checksum ... OK
    ## Flattened Device Tree blob at 02a00000
       Booting using the fdt blob at 0x2a00000
       Loading Kernel Image ... OK
       Loading Device Tree to 1fffa000, end 1ffffe47 ... OK
    
    Starting kernel ...
    
    Uncompressing Linux... done, booting the kernel.
    Booting Linux on physical CPU 0x0
    
    Linux version 3.14.0-g5ea3bc9 (jeckard@hotel.adral.analog.com) (gcc version 4.7.3 (Sourcery CodeBench Lite 2013.05-40) ) #1 SMP PREEMPT Thu May 1 08:26:35 EDT 2014
    
    CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
    
    CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
    
    Machine model: Xilinx Zynq ZC706
    
    bootconsole [earlycon0] enabled
    
    cma: CMA: reserved 40 MiB at 2d000000
    
    Memory policy: Data cache writealloc
    
    PERCPU: Embedded 7 pages/cpu @ec7c8000 s7680 r8192 d12800 u32768
    
    Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260624
    
    Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait devtmpfs.mount=0
    
    PID hash table entries: 4096 (order: 2, 16384 bytes)
    
    Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
    
    Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
    
    Memory: 992360K/1048576K available (3984K kernel code, 213K rwdata, 1512K rodata, 183K init, 126K bss, 56216K reserved, 270336K highmem)
    
    Virtual kernel memory layout:
    
        vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    
        fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    
        vmalloc : 0xf0000000 - 0xff000000   ( 240 MB)
    
        lowmem  : 0xc0000000 - 0xef800000   ( 760 MB)
    
        pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    
        modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    
          .text : 0xc0008000 - 0xc0566420   (5498 kB)
    
          .init : 0xc0567000 - 0xc0594e00   ( 184 kB)
    
          .data : 0xc0596000 - 0xc05cb400   ( 213 kB)
    
           .bss : 0xc05cb40c - 0xc05eacd4   ( 127 kB)
    
    Preemptible hierarchical RCU implementation.
    
    	Dump stacks of tasks blocking RCU-preempt GP.
    
    	RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
    
    RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
    
    NR_IRQS:16 nr_irqs:16 16
    
    slcr mapped to f0004000
    
    zynq_clock_init: clkc starts at f0004100
    
    Zynq clock init
    
    sched_clock: 16 bits at 54kHz, resolution 18432ns, wraps every 1207951633ns
    
    timer #0 at f0006000, irq=43
    
    Console: colour dummy device 80x30
    
    Calibrating delay loop... 1325.46 BogoMIPS (lpj=6627328)
    
    pid_max: default: 32768 minimum: 301
    
    Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
    
    Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
    
    CPU: Testing write buffer coherency: ok
    
    CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    
    Setting up static identity map for 0x3c3eb8 - 0x3c3eec
    
    L310 cache controller enabled
    
    l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72760000, Cache size: 512 kB
    
    CPU1: Booted secondary processor
    
    CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    
    Brought up 2 CPUs
    
    SMP: Total of 2 processors activated.
    
    CPU: All CPU(s) started in SVC mode.
    
    devtmpfs: initialized
    
    VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
    
    regulator-dummy: no parameters
    
    NET: Registered protocol family 16
    
    DMA: preallocated 256 KiB pool for atomic coherent allocations
    
    syscon f8000000.slcr: regmap [mem 0xf8000000-0xf8000fff] registered
    
    hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
    
    hw-breakpoint: maximum watchpoint size is 4 bytes.
    
    bio: create slab <bio-0> at 0
    
    SCSI subsystem initialized
    
    usbcore: registered new interface driver usbfs
    
    usbcore: registered new interface driver hub
    
    usbcore: registered new device driver usb
    
    media: Linux media interface: v0.10
    
    Linux video capture interface: v2.00
    
    Advanced Linux Sound Architecture Driver Initialized.
    
    Switched to clocksource ttc_clocksource
    
    NET: Registered protocol family 2
    
    TCP established hash table entries: 8192 (order: 3, 32768 bytes)
    
    TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
    
    TCP: Hash tables configured (established 8192 bind 8192)
    
    TCP: reno registered
    
    UDP hash table entries: 512 (order: 2, 16384 bytes)
    
    UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
    
    NET: Registered protocol family 1
    
    hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
    
    futex hash table entries: 512 (order: 3, 32768 bytes)
    
    bounce pool size: 64 pages
    
    msgmni has been set to 1490
    
    io scheduler noop registered
    
    io scheduler deadline registered
    
    io scheduler cfq registered (default)
    
    dma-pl330 f8003000.ps7-dma: Loaded driver for PL330 DMAC-2364208
    
    dma-pl330 f8003000.ps7-dma: 	DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
    
    e0001000.uart: ttyPS0 at MMIO 0xe0001000 (irq = 82, base_baud = 3124999) is a xuartps
    À¬Ëk½±•[ttyPS0] enabled
    console [ttyPS0] enabled
    
    bootconsole [earlycon0] disabled
    bootconsole [earlycon0] disabled
    
    [drm] Initialized drm 1.1.0 20060810
    drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_drv.c:axi_hdmi_platform_probe[176]
    platform 70e00000.axi_hdmi: Driver axi-hdmi requests probe deferral
    brd: module loaded
    loop: module loaded
    cdns-spi e0006000.spi: at 0xE0006000 mapped to 0xF0016000, irq=58
    cdns-spi e0007000.spi: at 0xE0007000 mapped to 0xF0018000, irq=81
    libphy: XEMACPS mii bus: probed
    xemacps e000b000.eth: pdev->id -1, baseaddr 0xe000b000, irq 54
    ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    ULPI transceiver vendor/product ID 0x0424/0x0007
    Found SMSC USB3320 ULPI transceiver.
    ULPI integrity check: passed.
    zynq-ehci zynq-ehci.0: Xilinx Zynq USB EHCI Host Controller
    zynq-ehci zynq-ehci.0: new USB bus registered, assigned bus number 1
    zynq-ehci zynq-ehci.0: irq 53, io mem 0x00000000
    zynq-ehci zynq-ehci.0: USB 2.0 started, EHCI 1.00
    hub 1-0:1.0: USB hub found
    hub 1-0:1.0: 1 port detected
    usbcore: registered new interface driver usb-storage
    usbcore: registered new interface driver usbserial
    usbcore: registered new interface driver usbserial_generic
    usbserial: USB Serial support registered for generic
    usbcore: registered new interface driver ftdi_sio
    usbserial: USB Serial support registered for FTDI USB Serial Device
    mousedev: PS/2 mouse device common for all mice
    i2c /dev entries driver
    i2c i2c-0: Added multiplexed i2c bus 1
    i2c i2c-0: Added multiplexed i2c bus 2
    at24 3-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write
    i2c i2c-0: Added multiplexed i2c bus 3
    i2c i2c-0: Added multiplexed i2c bus 4
    rtc-pcf8563 5-0051: chip found, driver version 0.4.3
    rtc-pcf8563 5-0051: rtc core: registered rtc-pcf8563 as rtc0
    i2c i2c-0: Added multiplexed i2c bus 5
    at24 6-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
    i2c i2c-0: Added multiplexed i2c bus 6
    i2c i2c-0: Added multiplexed i2c bus 7
    i2c i2c-0: Added multiplexed i2c bus 8
    pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548
    sdhci: Secure Digital Host Controller Interface driver
    sdhci: Copyright(c) Pierre Ossman
    sdhci-pltfm: SDHCI platform and OF driver helper
    mmc0: no vqmmc regulator found
    mmc0: no vmmc regulator found
    mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA
    platform leds.2: Driver leds-gpio requests probe deferral
    ledtrig-cpu: registered to indicate activity on CPUs
    hidraw: raw HID events driver (C) Jiri Kosina
    usbcore: registered new interface driver usbhid
    usbhid: USB HID core driver
    mmc0: new high speed SDHC card at address aaaa
    mmcblk0: mmc0:aaaa SB16G 14.8 GiB 
    adv7511-hdmi-snd adv7511_hdmi_snd.6: adv7511 <-> 75c00000.axi-spdif-tx mapping ok
     mmcblk0: p1 p2
    TCP: cubic registered
    NET: Registered protocol family 17
    Registering SWP/SWPB emulation handler
    regulator-dummy: disabling
    Console: switching to colour frame buffer device 240x75
    axi-hdmi 70e00000.axi_hdmi: fb0:  frame buffer device
    axi-hdmi 70e00000.axi_hdmi: registered panic notifier
    [drm] Initialized axi_hdmi_drm 1.0.0 20120930 on minor 0
    platform leds.2: Driver leds-gpio requests probe deferral
    rtc-pcf8563 5-0051: setting system clock to 2024-03-27 16:37:33 UTC (1711557453)
    ALSA device list:
      #0: HDMI monitor
    EXT4-fs (mmcblk0p2): warning: mounting fs with errors, running e2fsck is recommended
    EXT4-fs (mmcblk0p2): recovery complete
    EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
    VFS: Mounted root (ext4 filesystem) on device 179:2.
    Freeing unused kernel memory: 180K (c0567000 - c0594000)
    random: init urandom read with 84 bits of entropy available
    [00]¡Ë+‹é ureadahead main process (736) terminated with status 5
    [00]
    
    Last login: Mon Mar 25 09:55:25 EDT 2024 on tty1
    root@linaro-ubuntu-desktop:~# 

  • Your TES version seems good but please answer my 2nd question above.

  • I used the ADRV9009 Transceiver Evaluation Software to generate the files, Tools-->Create Script--> Init .c Files.

    Then I used the generated talise_config.c file with the no-OS project, excluding the original talise_config.c file. I also generate a TaliseStream.h file from TaliseStream.bin: both with the original and new file the result is the same.

    Note that the  generated talise_config.c has a syntax error.

    Thank you

    Maurizio

  • could you provide the generated .c/.h files that you are using? I would like to perform a diff with the existing ones and see of something is odd

  • The talise_config.c file I'm using is referred above.

    Also with the files provided in the no-OS release the behavior is the same.

    Thank you

    Maurizio

  • So Maurizio,

    I think the issue here is the following.

    TES generates 3 files, talise_config.c, talise_config.h and talise_config_ad9528.h.

    For (let's say) historical reasons, the way the adrv9009 project of no-OS is made, it ignores the last one of the above files and performs clocking initializations only for the 3 profiles that we support. So I'm thinking that the issues you are experiencing could be related to this, the fact that you try to use this particular ORX frequency that is not supported by the adrv9009 no-OS project as-is, it'd likely require modifications.

  • Thank you buha,

    so there is any chance that this modification will be available?

    In any case also if I compile the no-OS project with the supplied 491.52 MSPS profile commenting the line:
    #PROFILE = tx_bw100_ir122p88_rx_bw100_or122p88_orx_bw100_or122p88_dc122p88
    and uncommenting the line:
    PROFILE = tx_bw400_ir491p52_rx_bw200_or245p76_orx_bw400_or491p52_dc245p76
    in the src.mk file before launching the make command I get the same result.

    Is there something else to do in order to compile the no-OS project with the supplied 491.52MSPS profile?

    Thank you

    Maurizio



  • Is there something else to do in order to compile the no-OS project with the supplied 491.52MSPS profile?

    No, you're good, that's the only necessary step needed to change the profile. Just make sure to do 1. change profile, 2. make reset 3. make

    I get the same result.

    In that case we need to look into this because you are saying that the provided profile (so without generating anything new with TES) exhibits that behavior.

Reply Children