Post Go back to editing

no_OS ADRV9008-2 DMA_EXAMPLE not working

I'm trying to make the sample project ADRV9009 with DMA_EXAMPLE but it doesn't work.

I'm using these boards:

- EVAL-TPG-ZYNQ3 equivalent to ZC706 Xilinx

- ADRV9008-2 W/PCBZ from Analog Devices

I've used the FPGA project in "hdl/projects/adrv9009/zc706" and the firmware project in "no-OS/projects/adrv9009" with "DMA_EXAMPLE" defined.

I can't see neither a RF signal output nor the "DMA_EXAMPLE: address=0x7f170 samples=65536 channels=4 bits=16" on the serial output.

In the console output I see the following messages:

Hello
tx_clkgen: MMCM-PLL locked (61440000 Hz)
rx_os_clkgen: MMCM-PLL locked (61440000 Hz)
tx_adxcvr: OK (2457600 kHz)
rx_os_adxcvr: OK (2457600 kHz)
talise: Device Revision 192, Firmware 6.2.1, API 3.6.2.1
talise: Calibrations completed successfully
tx_jesd status:
Link is enabled
Measured Link Clock: 61.440 MHz
Reported Link Clock: 61.440 MHz
Lane rate: 2457.600 MHz
Lane rate / 40: 61.440 MHz
LMFC rate: 3.840 MHz
SYNC~: deasserted
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
rx_os_jesd status:
Link is enabled
Measured Link Clock: 61.440 MHz
Reported Link Clock: 61.440 MHz
Lane rate: 2457.600 MHz
Lane rate / 40: 61.440 MHz
LMFC rate: 3.840 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
tx_dac: Successfully initialized (122882080 Hz)

Any suggestion in order to try to find a solution to this issue?

Thank you

Maurizio Sonzogni

Top Replies

Parents Reply Children
  • Hi George,

    I don't know if I can continue with this thread or I must open another one, but I tried to run the DMA_EXAMPLE with both TX and ORX with 491,52 sampling rate and cannot get the result.

    To do this I created a new profile with the "ADRV9009 Transceiver Evaluation Software" and used the created talise_config.c file instead of that in the one present in the DMA_EXAMPLE project (see attachment)

    talise_config.c

    In this case I obtain this console output:

    Hello
    tx_clkgen: MMCM-PLL locked (245760000 Hz)
    rx_os_clkgen: MMCM-PLL locked (245760000 Hz)
    error: rx_os_adxcvr: adxcvr_init() failed
    Bye

    I tried also to use the headless.c file created by the "ADRV9009 Transceiver Evaluation Software" with a little modification in order to set the extra_spi and extra_gpio (see attachment)

    headless.c

    In this case I get this console output:

    ERROR: 321: Tx Profile IQrate and filter settings are not possible with current CLKPLL frequency
    ERROR: 180: Device not in radioOff/IDLE state. Error in TALISE_enableTrackingCals()

    What else must I modify in order to achieve TX and ORX channels at 491,52 sample rate?

    Thank you

    Maurizio

  • Hi  ,

    It is recommended to open a new thread for the new question since the initial problem is solved.

    Maybe the following forum is more appropriate for the new question:  Design Support ADRV9001 – ADRV9007 

    Regards,

    George