FMCW generation with Zynq and FMCOMMS2/3/4/5 with No-OS reference design

Tagging travisfcollins , maybe he has some suggestions on this matter.

- Iulia

Yes you can generate an FMCW signal from the transceiver. You could either create the waveform in software and transmit it through the DMA. Alternatively you could create custom IP to generate such a waveform.

With respect to the square and sawtooth waveform, these can be generated but they will not be very ideal just due to natural hardware limitation of the DAC. Sharp changes in signal amplitude tend to be shaped since they are very high frequency components.

-Travis

Thank you travisfcollins and iulia 

Yes you can generate an FMCW signal from the transceiver. You could either create the waveform in software and transmit it through the DMA.

--> You mean I can modify the code C which provided in reference design without modify the hardware in PL?  I saw in the HDL design, the IP AXI DMA have been installed.

Alternatively you could create custom IP to generate such a waveform.

-> It means that I will customize the IP AXI_AD9361 in Vivado, then re-generate the bitstream and export into Xilinx SDK? If yes, do you have any examples or references? 

After generation the signal FMCW, I would like to make a loop back and then process this signal (the signal processing of a simple FMCW radar application). So I don't know which way is better for me in this case?

Anw, I will first try to modify the C code in SDK and I will inform you asap.

I am looking forward to hearing from you.

Thank you very much for your support!

VPHAM589 said:

--> You mean I can modify the code C which provided in reference design without modify the hardware in PL?  I saw in the HDL design, the IP AXI DMA have been installed.

Yes. See the DMA_EXAMPLE build variant that loads data into memory for transmission.

VPHAM589 said:

-> It means that I will customize the IP AXI_AD9361 in Vivado, then re-generate the bitstream and export into Xilinx SDK? If yes, do you have any examples or references? 

You should not modify the axi_ad9361 core. You would connect your IP that creates the FMCW signal to it. We do not have specific examples for FMCW but other applications like Frequency hopping: Frequency Hopping Example Design [Analog Devices Wiki]

Can I ask why you chose No-OS over the Linux driver? The Linux driver will be far easier to use. No-OS is more meant for end system optimization.

-Travis

Hi,

According to your answer there is two solutions in my case:

1. The first one is just modify the PS (without modify PL). 

2. The second solution is modifying the PL (by adding an IP or block HDL code to generate FMCW)

I think I can start with the first solution (It could be the fastest way I can do now)

At the beginning, I don't know that I need to modify the reference design (in HDL) or no? according to the requirements of my project may be yes or may be no, I am not sure. So the thing I can do is start by HDL design then continue to by Bare-metal design. After that when everything works well, I can use Petalinux to build the Linux driver and booting with the image through SD card.

Thank you

VPHAM589 said:

At the beginning, I don't know that I need to modify the reference design (in HDL) or no

This depends on your requirements. If you are going to PetaLinux your probably want to use the Linux driver from the Kuiper Linux image and not No-OS.

-Travis

I have just take a look at the structure of No-Os in Xilinx SDK.

I have a questions about this structure.

After building no-os software for ad9631, I saw that there is no main.c in the src/ of app.

So If I want to generate a signal FMCW, I have to creat a new main.c in this folder to do it? or I must modify the main.c in ad9361/src/?

Thanks

Update main.c in the ad9361/src directory.

-Travis

Thank travisfcollins for your suggestions,
By debug the main.c on the mas-ter branch of No-OS 
https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9361/src/main.c
I have observed that the waveform can be loaded through the function "axi_dac_load_custom_data," where the value of a sine waveform is stored in a Look-Up Table (LUT) in the "dac_buffer" and loading by using AXI DMA.

In my current version (2019.2), I did not see this function, but I saw the function axi_dac_set_sine_lut which worked as the same purpose

I have take a look into the function (axi_dac_core.c) 

And I see that there are two variables: sine_lut and sine_lut_iq, Please tell me, in order to generate FMCW, which is the varible I need to modify? sine_lut or sine_lut_iq? how can I generate these values? using which tool?Matlab?

Many thanks

Yes, if I used Petalinux, I probably use the Linux driver. But I want to make sure that everything works well in PL and PS parts before building the Linux driver and booting with the image through SD card. 

If I used  the references design + linux driver at the beginning of this project, that means I don't need to modify in PL+PS(But In fact I need it).

In my case, with the reference HDL design (PL) and No-Os (PS), I don't think that can generate a FMCW without modify PS and PL part. So I choosed the No-OS is my approach.