AD9467 FMC Start Capturing data and see the output waveform in ADI IIO Oscilloscope

Hi,

Did you change anything on the software side? I'm not sure that the capture from the first scenario matches the Waveforms' displayed signal either.

Thanks,
Dragos

Hi,

No, we didn’t change anything on the software side as well as on hardware side. 

We created the no-OS(master branch) using make TINYIIOD=y flag and after that we connect the iio-oscilloscope and start capturing data in the oscilloscope.

Thanks

Hi,

From what I see in your previous thread.
Your sampling clock is 20MHz. According to the datasheet the minimum sampling clock should be 50MHz.
Your clock source is one of the the Analog Discovery 2 outputs, right? It's DAC is capable of 100MSPS, so, 50M is doable, but keep in mind that this setup is not exactly reliable. maybe not even as a proof of concept.
My suggestion is to use use ad9467 onboard clock and filter out samples, if bandwidth is your concern. Or use a more reliable clock source.

Andrei

Hi andrei_g and buha ,

Your suggestion is valid to use the ad9467 onboard clock frequency. Now, we will work on it to use the onboard clock frequency range between 50Mhz-250Mhz. After that, we will update you soon. 

If we want to look at the DDR data, can anyone tell me where the DDR data gets stored and in which format 16 or 32-bit?

Abbas047 ,

You already know the address, ADC_DDR_BASEADDR:

https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9467/src/devices/adi_hal/parameters.h#L52

Data is stored in 16-bit.

And as I said in the other thread, you may use the xilinx_capture.tcl script in no-OS repo to retrieve the data.

Hi,

One more aspect. You are trying to capture low frequency signals, right?
Take a look at:
AD9467 minimum analog input frequency
RE: DC coupling to AD9467
AD9467 KC705 Reference design
Request for review of ad9467 ADC front-end circuit
RE: set the analog input of AD9467 FMC + FPGA reference design to DC coupling

Andrei

Hi andrei_g and buha ,

We apologize for the delayed response; there are some problems on our end.
Although you advised using the ad9467 onboard clock frequency, you missed providing a link describing how to modify the configuration of the ad9467 onboard clock; instead, we used this source link.

https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467 

However, we get quite unpredictable results in Vitis Serial Terminal.

When we provide input from the ad9467_fmc.c using this function 

• ad9517_frequency(ad9517_device, 3, 150000000);
• ad9517_frequency(ad9517_device, 3, 250000000);

With the given inputs of 150 Mhz or 250 Mhz, we are getting the clock frequency in the region of 170-180 Mhz in Vitis Serial Terminal, why do these unpredictable results occur?

Please take a look at it to see why providing the clock input from the internal source code does not produce the desired results on the Vitis Serial Terminal or in case it's not the issue then provide another source that how to configure the ad9467 onboard clock.

Thanks

Abbas Ali
FPGA Engineer 

Hi Abbas,

Abbas047 said:

However, we get quite unpredictable results in Vitis Serial Terminal.

What do you mean? From one run to the other or from one setting to another?

Have you populated all c304 - c305 and c306 - 307? If so, you should drop one of the pairs(c306 - 307). If you take a look at the datasheet connecting all previous mentioned capacitors will short the out 3 and 5 of the clock chip.

We made the changes and tested things out too.
It seems that there is a limitation of the clock chip(or software config).
Desired freq vs obtained freq 
250M -> 250M
200M -> 250M
150M -> 124M

We will have a more in-depth look tomorrow.

Andrei

Hi andrei_g ,

I truly appreciate your response, and tomorrow we'll take an additional look. 

andrei_g said:

We will have a more in-depth look tomorrow.

Once you take a closer, more in-depth look tomorrow, kindly let me know as soon as you are able to.

Yes, we have populated all four caps (C304, C305, C306, and C307). You are right about this configuration, we are shorting output 3 and Output 5 of the Clock Generation IC. We will unpopulated C306 and C307 and will run the test again and update you soon.

It would be preferable if you could clear out our confusion on another question we have with an Analog Input Bandpass Filter.

Given the desired signal at 1 Mhz (50% duty cycle PWM signal), we knew that 1 Mhz is relatively low in comparison to 50 Mhz, but when we applied that 1 Mhz analog sinusoidal input to the ad9467, the analog input bandpass filter was fine.

Here is the picture:

• Results that are required to be displayed on the ADI IIO Oscilloscope are obtained at the clock frequency of 170-180 Mhz displayed on the Vitis Serial Terminal.

However, when we provided an analog signal other than sinusoidal input, the bandpass filter at the input side distorted our entire signal. As a result, the bandpass filter eliminated the majority of our signal's components. 

Here is the snapshot:

• Results that are required to be displayed on the ADI IIO Oscilloscope are obtained at the clock frequency of 170-180 Mhz displayed on the Vitis Serial Terminal.

Therefore, please provide the input filter configuration that how the resistors and capacitors will be utilized to retain the voltage waveform (square, triangular, etc) at 1Mhz and 50% duty cycle.

Thanks 
andrei_g and buha 

Abbas Ali 
FPGA Engineer

Hi andrei_g ,

Did you try to resolve the clock chip issue..?

Actually, we unpopulated pairs (C306-C307) and run the test again.

After these modifications, we obtain the outcomes shown in Vitis Serial Terminal. We achieve outcomes comparable to your ADI Team, but with a 10x reduction.

Desired freq vs obtained freq in Vitis Serial Terminal
250M -> 25M
200M -> 25M
150M -> 12.5M

Here are the issues:

• Why this 10x reduction occurs in these obtained frequencies?
  
• Is it still a problem to change the ad9467 onboard clock setup as described in this link:  https://wiki.analog.com/resources/fpga/xilinx/fmc/ad9467? We are getting stuck at this point, and the project is not moving forward, so if any changes need to be made to this link, kindly let me know as soon as possible.

Please take a close look at it and inform us as soon as you can.

Thanks 
Abbas Ali
FPGA Engineer