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Generates error in No-OS (2019_R2) using SDK 2019.1

Category: Software
Product Number: AD9467_EVAL_BOARD
Software Version: NO_OS (2019_R2)

Vivado Platform: 2019.1

SDK Platform: 2019.1

HDL Release Version: 2019_R2

No-OS Release Version: 2019_R2

Successfully, we created a hardware HDL(2019_R2) from analog devices sources ---> 

and it's bitstream generated successfully as mentioned in below figure

After, generation of bitstream we exported hardware to the SDK Platform 2019.1

Here, we insert all required API's from the analog devices sources --->

First of al, we choose the Xilinx Carrier in the app_config.h header file after addition of all API's to the SDK 2019.1.

Example for choosing the Xilinx carrier in the app_config.h header file. We uncomment the #define XILINX to declare it as a carrier.

Here are the issues:

  • Generates some issues in compat.h file.
  • Due to this errors in compat.h our SDK project does not build to run the ADC core ad9467 in testing mode.

Recent Milestone:

Test mode completion and it passed all the test pattern successfully.

Future Goals:

Using ad9467 evaluation board as a key component in our project and end the project as a patent.   

Microcontroller no-OS Drivers team, kindly have a look on my issues, Thanks
Otherwise, ad9467 evaluation board is useless in my upcoming projects because I done everything which you guys told me about Vivado Version and Release Version of analog devices and I installed these versions but still facing issues.

Kindly, need your team support as soon as possible.  

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  • My progress is in this direction:

    1. We followed all the steps given in this link - and create hdl design with a successful bitstream generated (No issue in HDL)
    2. After that, we followed the steps mentioned in to create a no-OS 2019_r2 on SDK 2019.1 but we facing issues with it. 

    Our approaches:

    1. First of all, we git cloned the and Switched the master branch to hdl_2019_r2 and no-OS_2019_R2. Build HDL_2019_r2 using Cygwin Terminal (Successfully bitstream generated). On the other hand, we tried to build the no-0S (2019_R2) in SDK using the command prompt as well as Windows PowerShell but we are facing issues with it.

    2. Again, we git cloned the master copy from similar above links. But, when we tried to Build HDL_master copy on Cyqwin Terminal it gives a version mismatch error due to Vivado 2019.1.


    We tried all the possibilities to get an error-free project, but we are still facing the above-mentioned issues in it. Kindly, go through all issues mentioned in this thread one by one.

    We are waiting for your response. 


    Abbas Ali

    FPGA Engineer