Post Go back to editing

DS28E05 - One wire memory driver

Category: Software

Hello,

we're developing a custom board and we have necessity to interface an STM32 microcontroller with DS28E05 one wire memory. Given the fact STM API doesn't cover one wire implementation, we need to implement our driver using bit-banging technique based on DS28E05 datasheet specification [1].

In this moment we are focused on implementing 'write memory' procedure described in Figure 6 of document [1]. In particular, this is our set of instructions:

  1. Follow initialization procedure ('Reset and Presence Pulse') described in Figure 9. This procedure is correctly implemented and it's working.
  2. Send to the memory 0xCC command, in order to skip ROM 64-bit ID settings.
  3. Send 0x55 command and follow the flowchart in Figure 6. So we send to the device: parameter byte, 0xFF byte, 2 data bytes.
  4. At this point the flowchart states 2 data bytes must be checked through a read byte command. This is the point we are struggling: we always get a 0xFF byte after a readback.

Furthermore, we want to illustrate how we implemented the low level driver functions: Write-One, Write-Zero and Read Bit waveforms described in Figure 10. We noticed that these waveforms are also described in document [2].

- Write-One -

  • Drive bus LOW,
  • Delay: 1 us,
  • Drive bus HIGH,
  • Delay: 15 us.

- Write-Zero -

  • Drive bus LOW,
  • Delay: 10 us,
  • Drive bus HIGH,
  • Delay: 6 us.

- Read bit -

  • Drive bus LOW,
  • Delay: 1 us,
  • Set bus in input mode (at least 6 us for our STM32)
  • Delay: 1 us,
  • Sample bus
  • Delay: 15 us
  • Set bus in output mode

Could you give us some suggestions to improve our implementation and make the driver work?

Thank you for any help and suggestion you will provide. 

Best wishes,

Gabriele Ghetti

[1] https://www.analog.com/media/en/technical-documentation/data-sheets/DS28E05.pdf

[2] https://pdfserv.maximintegrated.com/en/an/AN126.pdf

Parents Reply
  • Fortunately we managed to implement a first working version of the driver.

    The main issue of this memory is that it only supports 'overdrive' mode. Overdrive means protocol delays are very tiny and strict (compared to standard one-wire protocol). So in order to achieve microseconds delays, especially in the read bit command, we had to optimize the code working directly with uC registers.

    Regards

    GG

Children
No Data