Hi,
Do you have No-OS STM32F4X and ARDV9003 project sample?
Best Regards
ADRV9003
Production
The ADRV9003 is a highly integrated RF transceiver that has a single-channel transmitter, dual-channel receivers, integrated synthesizers, and digital...
Datasheet
ADRV9003 on Analog.com
Hi,
Do you have No-OS STM32F4X and ARDV9003 project sample?
Best Regards
Nope, you need programmable logic to process data to/from adrv9001 family chips. See the document provided by ConradCollins above.
Hi, When i try to build STM32 (NO-OS) (Ubuntu); I have "No rule to make target" error for xilinx_axi_io.c file in generic.mk:293: recipe for target 'all' failed.
So BilginV I don't get it, do you use STM32 or a pure FPGA hardware ?
Our device is pure FPGA not SoC
STM32
Is STM32 just for the proof of concept, whether you can change carrier frequency and AGC over SPI ?
If you want to use STM32 as a processor you'd have to modify these files:
https://github.com/analogdevicesinc/no-OS/tree/master/projects/adrv9001/src/hal
Specifically no_os_platform.c/.h and parameters.h
But still you'd need a digital interface to an FPGA like I said in my first reply.
I would recommend against such a dual design. Get a SoC that integrates the processor and FPGA as our reference project shows. I'm skeptical that we will ever provide a reference project for a dual design (STM32 processor + separate FPGA).
If you want to use STM32 as a processor you'd have to modify these files:
https://github.com/analogdevicesinc/no-OS/tree/master/projects/adrv9001/src/hal
Specifically no_os_platform.c/.h and parameters.h
But still you'd need a digital interface to an FPGA like I said in my first reply.
I would recommend against such a dual design. Get a SoC that integrates the processor and FPGA as our reference project shows. I'm skeptical that we will ever provide a reference project for a dual design (STM32 processor + separate FPGA).
Hi, since we couldnt find any solution with pure FPGA. We have tried to control ADRV9003 via stm32. we dont have dual architecture. STM32 will show the the solution which can be implemented in the fpga (RTL). There shall be some solution which lead us to use multiple ADRV9003 with single FPGA. Also, we want use our own DSP IPs to enhance performance.
Best Regards