ad9361 received IQ samples missing

Hi ascialdo ,

It seems that the data you are getting contains just a part of the sine wave. Have you tried to retrieve the data using the script in the following Wiki page?

https://wiki.analog.com/resources/no-os/dac_dma_example

Regards,

George

Hello George, actually no because i am not on a xilinx FPGA, so I can't run the script.

So i have a for loop that reads the memory location as i said before, and is sending each value through UART.

ascialdo said:

core acquires repeatedly the samples between 97 and 128, which are samples that I clearly wrote inside the DDR address space of the DAC? Am I missing something?

At a first glance looks like a bug. The engineer who worked on axi_dmac left the company. Someone will investigate, a quick answer is not possible.

Andrei

I have just checked the values of those two registers by the way, and it is 0x02, which corresponds to input DMA as expected. I will keep investigating by the way, I will let you know if i find something else. Tanks a lot anyway

Hi,

The waveform you attached for the pluto looked pretty clean, that is why I was presumed it was from a DDS source.
From what release have you started porting ADI code to Microchip's build process, I'm interested for testing the above dma case.

Andrei

Hi Andrei, I have started from the 2019_r2 source. I am looking more in details at the output of the ad9361_init() function.

Why the cf-ad9361-lpc frequency is set at 0 Hz? And when I initialize the dac core instead is 144 MHz.

I have also noticed that every time I restart, these frequencies are always set at different values.

Do you think that posting here the full output could be of help?

Regards

Something is wrong there.
That clock is a ratio between the PS clock and the ADC clock. It is stored in reg 

for adc.
https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt#understanding_fmcomms2_clock_routing
In the link above is the clock path on our reference designs.
What is your PS(axi) clock?
Are you generating the clock for TX? Our design uses an l_clk(local clock). The tx clock should be an echoed clock of the rx one.

Andrei

The AXI clock is 50 MHz. Could this be a problem?

For the TX clock I use the l_clk, that is coming from the rx_clk_in_p/n, as in your reference design

Antonio

Typically our axi clock is 100M, even if yours is not correctly reported(100 instead of 50), the reported clock ratio should be double, not zero.
Can you manually read the value stored in this registers for ADC and DAC?

You manage to capture some data, which could not be possible if your adc path does not have clock, this confuses me.

Andrei

So I have changed the AXI clock to 100 MHz. The behaviour didn't change

By reading the content of the register 0x54 I get:

DAC Core: 0x9c14

ADC Core: 0x9c4b

From my calculations, if you are using axi clock = 100MHz
your sampling clock is aprox 61.4M.

If this is right. something in your no-OS is not correctly configured, resulting in the 0Hz.

Andrei

Given that i did not change anything inside the no-os code, i have to assume that the design is not working correctly when synthesizing it for another FPGA. In case I find out what is the issue, i will post it on this thread. Thanks anyway for your support.

Best regards,

Antonio

Given that i did not change anything inside the no-os code, i have to assume that the design is not working correctly when synthesizing it for another FPGA. In case I find out what is the issue, i will post it on this thread. Thanks anyway for your support.

Best regards,

Antonio