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I'm using the fmcomms5 with the zc706 board. I downloaded from the github repository the vhd (2021.r1) and the no-os(2021.r1). , . 
My first task is to receive and transmit a sine wave. 
In reception, I have not encountered any problems. I follow the examples and I'm able to receive from all the two chips both channels and I can save and see the received signals both in a buffer (adc_buffer) and in DDR. 

Now I would like to know how I can transmit custom data save in DDR. I tried to follow the same order and procedure used in the reception but it doesn't work. 

To follow a summary of the functions called and the order of the main.c with the relative problems encountered.

  • chip 1 Initialization : 

	default_init_param.spi_param.extra = &xil_spi_param;
	default_init_param.spi_param.platform_ops = &xil_spi_ops;
// NOTE: The user has to choose the GPIO numbers according to desired
// carrier board.
	default_init_param.gpio_resetb.number = GPIO_RESET_PIN;
	default_init_param.gpio_sync.number = GPIO_SYNC_PIN;
	default_init_param.gpio_cal_sw1.number = GPIO_CAL_SW1_PIN;
	default_init_param.gpio_cal_sw2.number = GPIO_CAL_SW2_PIN;
	default_init_param.rx1rx2_phase_inversion_en = 1;
	default_init_param.xo_disable_use_ext_refclk_enable = 1;
	default_init_param.rx_synthesizer_frequency_hz = rx_carrier_freq1;
	default_init_param.tx_synthesizer_frequency_hz = tx_carrier_freq1;

	ad9361_init(&ad9361_phy, &default_init_param);

	ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
	ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);

  • chip 2 Initialization : 
  • axi_dmac_init(&rx_dmac, &rx_dmac_init);
  • axi_dmac_init(&tx_dmac, &rx_dmac_init);
  • At this point I change the parameter for the first and second chip for my task (change tx and rx sampling freq, bandwidth...)

  • Now I have done


axi_dac_init(&ad9361_phy->tx_dac, &tx_dac_init);
axi_dac_init(&ad9361_phy_b->tx_dac, &tx_dac_init);

axi_dac_set_datasel(ad9361_phy->tx_dac, -1, AXI_DAC_DATA_SEL_DMA);
axi_dac_set_datasel(ad9361_phy_b->tx_dac, -1, AXI_DAC_DATA_SEL_DMA);

I saved my custom sine wave in DDR and then I try to transmit:

unsigned long long *puntatore_DDR_DAC= (unsigned long long*)0xA000000;

				for(int i = 0; i< 1024 ;i++){
					*(puntatore_DDR_DAC+i) = my_sinelut_iq[i];

				//check_dac_init = axi_dac_init(&ad9361_phy_b->tx_dac, &tx_dac_init);
				//printf("\n\ncheck dac init = %ld\n\n",check_dac_init);
				//axi_dac_set_datasel(ad9361_phy_b->tx_dac, -1, AXI_DAC_DATA_SEL_DMA);

				struct axi_dma_transfer trasmissione = {
						// Number of bytes to write/read
						.size = 1600,
						// Transfer done flag
						.transfer_done = 0,
						// Signal transfer mode
						.cyclic = CYCLIC,
						// Address of data source
						.src_addr = (uintptr_t)DAC_DDR_BASEADDR,
						// Address of data destination
						.dest_addr = 0
				/* Transfer the data. */
				axi_dmac_transfer_start(tx_dmac, &trasmissione);

				axi_dmac_transfer_wait_completion(rx_dmac, 500);

				/* Flush cache data. */

My questions are:


is the sequence of the called function correct? I have a problem because it seems that the first chip dac initialization does not work, I can see nothing from the first chip. I can see a wrong transmission when I change the order in main.c as follow:
- initialization chip 1
-axi_dac_init() chip 1
-axi_dac_set_datasel chip 1
-initialization chip 2
-axi_dac_init() chip 2
-axi_dac_set_datasel chip 2
-axi_dmac_init  for tx core
-axi_dmac_init  for rx core


the transmitted signal using the main.c sequence of Q1 is not the sine wave that I expect and I save it in DDR. someone can help me to understand how to use correctly the function in order to save and transmit a simple sine wave saved in DDR?
I'm using the DAC_DDR_BASEADDR and I want to transmit a signal saved from that base address

Thank you all 
Best regards.

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  • Hi   

    I am writing to provide an update on the issue we discussed earlier regarding the MCS. I have identified the problem and it was related to the function that controls the GPIO[45] within the MCS function not working properly. To resolve this issue, I used the classic Xilinx functions for the GPIO, which resulted in GPIO[45] moving correctly and SYNC_IN pulse being sent accurately. I have confirmed this with an oscilloscope.

    However, a new problem has arisen where after the second pulse, the two output clocks observed with the oscilloscope do not overlap in phase, but are positioned with a fixed delay of approximately 12 ns when the clk_output_mode_select is set to division 16. However, I have found that regardless of the division value, the two clocks never synchronize perfectly in phase.

    I am unsure what could be causing the incorrect synchronization and would appreciate your insight into the matter. Please let me know if there is anything else I can do to resolve this issue.

    Thank you for your time and assistance.

    Best regards



  • Hi  ,

    Is this still an issue? Have you tried running the DMA or IIO example with the current no-OS and hdl branches?

    Thank you for your feedback regarding the GPIO not working correctly! There was a line of code missing, that sets the direction of the SYNC signal. The problem should be fixed now on the master no-OS branch.