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JESD204B configuration when using lanerate as 5GPS on AD9081

Category: Software

Hi everyone,
I am receiving no output signal when I set my lane rate to 5GSPS, using the jesd mode helper tool: My configuration is as follows:

TX side: JESD MODE Number 6 txBW 200.0 Total interpolation 16, Coarse Int = 8, Fine Int =2, M=2, L=2, F=2, S=1, K=32, N=16, NP =16, Lane rate: 5.0 

RX side: JESD MODE Number 7.00 txBW 203.5 Total interpolation 16, Coarse Int = 4, Fine Int =4, M=2, L=2, F=2, S=1, K=32, N=16, NP =16, Lane rate: 5.0 

I configure the timing_constr.xdc file on the FPGA design to as follows:

# Primary clock definitions
create_clock -name refclk      -period 4 [get_ports fpga_refclk_in_p]

# device clock
create_clock -name tx_device_clk     -period 8 [get_ports clkin6_p]
create_clock -name rx_device_clk     -period 8 [get_ports clkin10_p]

On the NO-OS side i do the following changes in the app_config.h:

#define AD9081_DAC_FREQUENCY	4000000000
#define AD9081_ADC_FREQUENCY	4000000000
#ifdef QUAD_MXFE
#define AD9081_ADC_NYQUIST_ZONE	{1, 1, 1, 1}
#else
#define AD9081_ADC_NYQUIST_ZONE	{0, 0, 0, 0}
#endif

/* TX path */

#define AD9081_TX_JESD_MODE		6
#define AD9081_TX_JESD_SUBCLASS		1
#define AD9081_TX_JESD_VERSION		1
#define AD9081_TX_JESD_M		2
#define AD9081_TX_JESD_F		2
#define AD9081_TX_JESD_K		32
#define AD9081_TX_JESD_N		16
#define AD9081_TX_JESD_NP		16
#define AD9081_TX_JESD_CS		0
#define AD9081_TX_JESD_L		2
#define AD9081_TX_JESD_S		1
#define AD9081_TX_JESD_HD		1
#ifdef QUAD_MXFE
#define AD9081_TX_LOGICAL_LANE_MAPPING	{0, 1, 2, 3, 4, 5, 6, 7}
#else
#define AD9081_TX_LOGICAL_LANE_MAPPING	{0, 2, 7, 7, 1, 7, 7, 3}
#endif

#define AD9081_TX_MAIN_INTERPOLATION	8
#define AD9081_TX_CHAN_INTERPOLATION	2
#define AD9081_TX_MAIN_NCO_SHIFT	{1500000000, 0, 0, 0}
#define AD9081_TX_CHAN_NCO_SHIFT	{0, 0, 0, 0, 0, 0, 0, 0}
#define AD9081_TX_CHAN_GAIN		{2048, 0, 0, 0, 0, 0, 0, 0}

#define AD9081_TX_DAC_CHAN_CROSSBAR	{0x1, 0x2, 0x4, 0x8}

/* RX path */

#define AD9081_RX_JESD_MODE		7
#define AD9081_RX_JESD_SUBCLASS		1
#define AD9081_RX_JESD_VERSION		1
#define AD9081_RX_JESD_M		2
#define AD9081_RX_JESD_F		2
#define AD9081_RX_JESD_K		32
#define AD9081_RX_JESD_N		16
#define AD9081_RX_JESD_NP		16
#define AD9081_RX_JESD_CS		0
#define AD9081_RX_JESD_L		2
#define AD9081_RX_JESD_S		1
#define AD9081_RX_JESD_HD		1
#ifdef QUAD_MXFE
#define AD9081_RX_LOGICAL_LANE_MAPPING	{0, 1, 2, 3, 4, 5, 6, 7}
#else
#define AD9081_RX_LOGICAL_LANE_MAPPING	{2, 0, 7, 7, 7, 7, 3, 1}
#endif
#define AD9081_RX_LINK_CONVERTER_SELECT	{0, 1, 2, 3, 8, 9, 10, 11, 0, 0, 0, 0, 0, 0, 0, 0}

#define AD9081_RX_MAIN_DECIMATION	{4, 4, 0, 0}
#define AD9081_RX_CHAN_DECIMATION	{4, 4, 0, 0, 0, 0, 0, 0}
#define AD9081_RX_MAIN_ENABLE		{1, 1, 0, 0}
#define AD9081_RX_CHAN_ENABLE		{1, 1, 0, 0, 0, , 0, 0}
#define AD9081_RX_MAIN_NCO_SHIFT	{1500000000, 0, 0, 0}
#define AD9081_RX_CHAN_NCO_SHIFT	{0, 0, 0, 0, 0, 0, 0, 0}

also I change the app_jesd_init function inputs to as follows:

app_jesd_init(jesd_clk, 250000, 125000,125000, 5000000,5000000);

the log that is printed is as follows:

rx_adxcvr: OK (5000000 kHz)
tx_adxcvr: OK (5000000 kHz)
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (5000000 kHz)
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (5000000 kHz)
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (5000000 kHz)
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (5000000 kHz)
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (5000000 kHz)
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (5000000 kHz)
ad9081_jesd_rx_link_status_print: JESD RX (JTX) Link1 in DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid
DAC IRQ status 0xf043000000
IRQ_STATUS0: 0x0
ad9081_multichip_sync:2
ad9081_multichip_sync:3
tx_adxcvr: OK (5000000 kHz)
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (5000000 kHz)
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_jesd status:
		Link is enabled
		Measured Link Clock: 250.021 MHz
		Reported Link Clock: 125.000 MHz
		Lane rate: 50000.000 MHz
		Lane rate / 40: 125:000 MHz
		LMFC rate: 7.812 MHz
		SYNC~: deasserted
		Link status: ILAS
		SYSREF captured: Yes
		SYSREF alignment error: No
rx_jesd status:
		Link is enabled
		Measured Link Clock: 250.021 MHz
		Reported Link Clock: 125.000 MHz
		Lane rate: 50000.000 MHz
		Lane rate / 40: 125:000 MHz
		LMFC rate: 7.812 MHz
		Link status: DATA
		SYSREF captured: Yes
		SYSREF alignment error: No
tx_dac: Succesfully initialized (5000042724 Hz)
rx_adc: Succesfully initialized (5000042724 Hz)	

As it can be seen the IRQ_STATUS0 is 0 and i cannot see any output waveform at the frontend. Is there something that I am doing wrong or have I missed something that I should set.
For both the NO-OS and the HDL i am using the 2021_R1 branch from github.

Any help would be appreciated

Top Replies

    •  Analog Employees 
    Apr 10, 2023 in reply to aamirsaeed +1 suggested

    Hi ,

    This is a complex question, normally we offer the reference designs that are a functional reference to start a custom project on, we can't possibly go into details of custom designs.…