I'm using ADRV9002 with Zynq MPSoC. I used HDL reference design and "no_os_master" example application. I generate a profile with TES GUI which is 61.44 MSPS and 10 MHz BW. When I use this configuration with Eval Board ADRV9001, Data Rate and BW are correct. But I also use the same configuration with my custom board and when I use my custom board, Data Rate and BW are the half of the expected values. For the custom board, I only disable RX2-TX2. Other things on HDL Reference Design and application code, are the same as Eval Board. What could be the reason for that? In my opinion, I may not configure LVDS Lanes as DDR. But for eval board, configuration works as expected. Do you have any opinion to check about application code?