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AD9528 Recommended for New Designs
The AD9528 is a two-stage PLL with an integrated JESD204B/JESD204C SYSREF generator for multiple device synchronization. The first stage phase-locked loop...
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The AD9258 is a dual, 14-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC). The AD9258 is designed to support communications applications...
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AD9258 on Analog.com

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AD9528 write register invalid



		

			

									
					    Shun21
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jul 12, 2022 
				
			
			
		
    

				
		
    
		    		    
		    
		    		            		        
    Category: Hardware
    
    		        		            		    
    Product Number:  AD9528 
    
    		        		        		        
    Software Version: Qt 5.12.11
    
    		    		    	
			
    1、In my ad9258 chip, the 8th pin VCXO_VT pin is always low voltage. The second pin (rfa) and the third pin (rfa_n) have differential signal input.
    

    2、No matter how the register value is modified, out13 always outputs the reference clock input by rfa, but if I write a reset command to 0x000, all registers return to their default values. In addition, how to modify other register values, it seems that the function has not changed. After several times of reading and writing the register, confirm that the register is readable and writable, and after writing the register, write the update command to the box 00f register.
    

    Schematic：
    

     
    

    Register Configuration Order：
    

     
    
								
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
			                            
                        
                on Jul 12, 2022 7:20 PM
            
            
					
      
	
      

		
		
      
					
      Hi,
      

      in the future, please entry questions related to the AD9528 functionality in the Clock and Timing section of Engineer Zone.
      

      I introduced the register values you gave me into the AD9528 evaluation software. I saw the VCXO has 100MHz. This makes REFA to be 50MHz based on your settings:
      

       
      

      PLL2 is not set correctly, so PLL2 should not function. Then, you selected the PLL1 feedback clock to come from PLL2 feedback clock, which does not work. I recommend changing the PLL1 feedback clock to come from the VCXO, bit 2 in register 0x109 set to 1.
      

      This should help you get PLL1 locked and obtain a clock at OUT13. I attach the stp file I created based on the register configuration you gave. It reflects the change in register 0x109, bit 2.
      

      



      
    
      
        Fullscreen
        AD9528_setup_20220712.stp.txt
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      <header>
product = AD9528
softwareversion = 1.0.0.3
</header>

<detailed setup information>
-- PLL1 --
 - Ref A -
    Input Freq: 50.0 MHz
    Ra: 1
    PFD Freq: 50.0 MHz
 - Ref B -
    Powered Down
 - Clk In -
    Osc Freq: 100.0 MHz
    N1: 2
    PFD Freq: 50.0 MHz
------------------
-- PLL2 --
    Input Freq: 100.0 MHz
    R2: /1
    PFD Freq: 100.0 MHz
    N2: 21
    Dist Freq: 2.1 GHz
    M: 4
    VCO Freq: 8.4 GHz
----------------------
-- SysRef --
    Source: Internal Generation
    Freq: 781.25 kHz
----------------------
-- Distribution --
    Input Source: PLL2
    Input Freq: 2.1 GHz
 - Out 0 -
    Input Source: D0
    D0:5
    Output Freq: 420.0 MHz
 - Out 1 -
    Input Source: Sysref
    Output Freq: 781.25 kHz
 - Out 2 -
    Input Source: D2
    D2:5
    Output Freq: 420.0 MHz
 - Out 3 -
    Input Source: Sysref
    Output Freq: 781.25 kHz
 - Out 4 -
    Input Source: D4
    D4:5
    Output Freq: 420.0 MHz
 - Out 5 -
    Input Source: Sysref
    Output Freq: 781.25 kHz
 - Out 6 -
    Input Source: D6
    D6:5
    Output Freq: 420.0 MHz
 - Out 7 -
    Input Source: Sysref
    Output Freq: 781.25 kHz
 - Out 8 -
    Input Source: D8
    D8:5
    Output Freq: 420.0 MHz
 - Out 9 -
    Input Source: Sysref
    Output Freq: 781.25 kHz
 - Out 10 -
    Input Source: D10
    D10:5
    Output Freq: 420.0 MHz
 - Out 11 -
    Input Source: Sysref
    Output Freq: 781.25 kHz
 - Out 12 -
    Input Source: PLL1
    Output Freq: 100.0 MHz
 - Out 13 -
    Input Source: PLL1
    Output Freq: 100.0 MHz
----------------------
</detailed setup information>

<registers>
Register (Hex),	Value (Hex),	Value (Dec)
0x0,		0x00,		0
0x1,		0x00,		0
0x3,		0x05,		5
0x4,		0xFF,		255
0x5,		0x00,		0
0x6,		0x03,		3
0xa,		0x00,		0
0xb,		0x00,		0
0xc,		0x56,		86
0xd,		0x04,		4
0xf,		0x00,		0
0x100,		0x01,		1
0x101,		0x00,		0
0x102,		0x00,		0
0x103,		0x00,		0
0x104,		0x02,		2
0x105,		0x00,		0
0x106,		0x0A,		10
0x107,		0x03,		3
0x108,		0x28,		40
0x109,		0x04,		4
0x10a,		0x02,		2
0x10b,		0x00,		0
0x200,		0xE6,		230
0x201,		0x15,		21
0x202,		0x03,		3
0x203,		0x01,		1
0x204,		0x04,		4
0x205,		0x2A,		42
0x206,		0x00,		0
0x207,		0x02,		2
0x208,		0x14,		20
0x209,		0x00,		0
0x300,		0x00,		0
0x301,		0x00,		0
0x302,		0x04,		4
0x303,		0x40,		64
0x304,		0x00,		0
0x305,		0x00,		0
0x306,		0x00,		0
0x307,		0x00,		0
0x308,		0x04,		4
0x309,		0x40,		64
0x30a,		0x00,		0
0x30b,		0x00,		0
0x30c,		0x00,		0
0x30d,		0x00,		0
0x30e,		0x04,		4
0x30f,		0x40,		64
0x310,		0x00,		0
0x311,		0x00,		0
0x312,		0x00,		0
0x313,		0x00,		0
0x314,		0x04,		4
0x315,		0x40,		64
0x316,		0x00,		0
0x317,		0x00,		0
0x318,		0x00,		0
0x319,		0x00,		0
0x31a,		0x04,		4
0x31b,		0x40,		64
0x31c,		0x00,		0
0x31d,		0x00,		0
0x31e,		0x00,		0
0x31f,		0x00,		0
0x320,		0x04,		4
0x321,		0x40,		64
0x322,		0x00,		0
0x323,		0x00,		0
0x324,		0x20,		32
0x325,		0x00,		0
0x326,		0x00,		0
0x327,		0x20,		32
0x328,		0x00,		0
0x329,		0x00,		0
0x32a,		0x00,		0
0x32b,		0x00,		0
0x32c,		0x00,		0
0x32d,		0x00,		0
0x32e,		0x00,		0
0x400,		0x00,		0
0x401,		0x00,		0
0x402,		0x00,		0
0x403,		0x00,		0
0x404,		0x04,		4
0x500,		0x10,		16
0x501,		0x00,		0
0x502,		0x00,		0
0x503,		0xFF,		255
0x504,		0xFF,		255
0x505,		0x00,		0
0x506,		0x00,		0
0x507,		0x00,		0
0x508,		0x00,		0
0x509,		0x00,		0
</registers>

<frequencies>
50000000;122880000;100000000;768000
</frequencies>

      

      


      

      I looked over the schematic and the VCXO connection to the AD9528 reflects the single ended pin VCXO_INP setting in the configuration. 
      

      Read the registers 0x508 and 0x509 to get info about how the AD9528 sees REFA, VCXO and PLL1 lock/unlock status.
      

      If you need help setting the PLL2 and/or SYSREF generator, just tell me what outputs you need to obtain and I'll create a configuration for you
      

      Petre
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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													0
							
			
				
									
							        
			
			
			
        
            
			                            
                        
                on Jul 13, 2022 5:14 PM
            
            
												
						in reply to pminc48
					
									
        
	
        

		
		
        
					
        Hi
        

        Thank you Mr Petre.
        

        I configured the register according to the way you gave, but still did not solve the problem. My register configuration order is from 0x000 to 0x509, and finally 0x0000f01. If the register configuration has nothing to do with the order, I have to consider whether there is a problem with the schematic design.Thanks again Petre for being able to answer my question.
        

         

        

         
        

         
        

        

        

         
        

         
        

        Shun
        

        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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        •  Analog Employees  
        
            
			                            
                        
                on Jul 15, 2022 5:44 PM
            
            
												
						in reply to Shun21
					
									
        
	
        

		
		
        
					
        HI,
        

        I recommended in my previous post to check the status registers: Read the registers 0x508 and 0x509 to get info about how the AD9528 sees REFA, VCXO and PLL1 lock/unlock status.
        

        I do not see any report on this.
        

        Please check the differential voltage on REFA pins and verify it meets these conditions:
        

         
        

        Petre
        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
						
						
				
				
		
		
        
			
		
        
	
        

        

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