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ADRV9009 - New profile with external ref_clk

Hi,

I am using external ref_clk at 121.333 MHz and I am trying to work with a new profile. Even if I don't face with any problem at profile generation at matlab and .c file generation at talise, I can't take proper data from RX due to some "sysref" problems. I am attaching the profile files and .c files to the post with the uart screen.

Because of the talise's connection problem with ZCU102 board, I generate .c files offline and I guess ad9528 configurations doesn't writed to .c file. So I take as reference links that below for ad9528 configuration.

https://wiki.analog.com/resources/eval/user-guides/rf-trx-vcxo-and-profiles#requesting_deframer_framer_lanerate_failed

https://ez.analog.com/wide-band-rf-transceivers/design-support-ad9371/w/documents/10080/ad9371-evaluation-board-vcxo-selection

Why TAL_FRAMER_A status 0x27 instead of 0x05? What is worng with profile?

adrv9009.zip



fix
[edited by: ee-bhan at 10:34 AM (GMT -4) on 30 Jun 2022]
[locked by: buha at 6:53 AM (GMT -4) on 26 Sep 2022]

Top Replies

    •  Analog Employees 
    Jul 26, 2022 +1 suggested

    Hi ,

    I've tried your profile and code on hardware based on 2019_R2 branch, however I got a different result:

    Hello
    rx_clkgen: MMCM-PLL locked (121333000 Hz)
    tx_clkgen: MMCM-PLL locked (121333000…

Parents
  • Hi ,

    I've tried your profile and code on hardware based on 2019_R2 branch, however I got a different result:

    Hello
    rx_clkgen: MMCM-PLL locked (121333000 Hz)
    tx_clkgen: MMCM-PLL locked (121333000 Hz)
    rx_os_clkgen: MMCM-PLL locked (121333000 Hz)
    rx_adxcvr: OK (4853320 kHz)
    tx_adxcvr: OK (4853320 kHz)
    rx_os_adxcvr: OK (4853320 kHz)
    talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.521121266925568005
    ERROR: 247: TALISE_waitArmCmdStatus() failed due to thrown ARM error. ARM time out 
    error: TALISE_waitInitCals() failed
    Bye
    

    What I did was to use the profile from the archive and replace the app_clocking.c file from the archive (with some adaptations, I think you put a file from master, not from 2019_R2 in the archive):

    diff --git a/projects/adrv9009/src/app/app_clocking.c b/projects/adrv9009/src/app/app_clocking.c
    index 7a86dc213..4bf741d39 100644
    --- a/projects/adrv9009/src/app/app_clocking.c
    +++ b/projects/adrv9009/src/app/app_clocking.c
    @@ -124,7 +124,6 @@ adiHalErr_t clocking_init(uint32_t rx_div40_rate_hz,
                     .pll1_ref_prio_ctrl = 0xE5,
                     .sync_pin_mode = 0x1,
                     .high_performance_mode_clock_dist_en = true,
    -                .high_performance_mode_pll_vco_en = true,
                     .pulse_gen_mode = 0x0,
             };
     
    @@ -286,36 +285,49 @@ adiHalErr_t clocking_init(uint32_t rx_div40_rate_hz,
             ad9528_channels[13].driver_mode = DRIVER_MODE_LVDS;
             ad9528_channels[13].divider_phase = 0;
             ad9528_channels[13].signal_source = SOURCE_VCO;
    +        //user conf.
    +        ad9528_channels[13].channel_divider = 5;
     
             // fpga device clock
             ad9528_channels[1].output_dis = 0;
             ad9528_channels[1].driver_mode = DRIVER_MODE_LVDS;
             ad9528_channels[1].divider_phase = 0;
             ad9528_channels[1].signal_source = SOURCE_VCO;
    +        //user conf.
    +        ad9528_channels[1].channel_divider = 5;
     
             // adrv9009 sysref
             ad9528_channels[12].output_dis = 0;
             ad9528_channels[12].driver_mode = DRIVER_MODE_LVDS;
             ad9528_channels[12].divider_phase = 0;
             ad9528_channels[12].signal_source = SOURCE_SYSREF_VCO;
    +        //user conf.
    +        ad9528_channels[12].channel_divider = 5;
     
             // fpga sysref
             ad9528_channels[3].output_dis = 0;
             ad9528_channels[3].driver_mode = DRIVER_MODE_LVDS;
             ad9528_channels[3].divider_phase = 0;
             ad9528_channels[3].signal_source = SOURCE_SYSREF_VCO;
    +        //user conf.
    +        ad9528_channels[3].channel_divider = 5;
    +
    +        // user
    +        //ad9528_param.pdata->ref_mode = REF_MODE_REVERT_TO_REFA;
     
             // ad9528 settings
             ad9528_param.pdata->spi3wire = 0;
    -        ad9528_param.pdata->vcxo_freq = 122880000;
    +        ad9528_param.pdata->vcxo_freq = 121333000;
             ad9528_param.pdata->refa_en = 1;
             ad9528_param.pdata->refa_diff_rcv_en = 1;
             ad9528_param.pdata->refa_r_div = 1;
             ad9528_param.pdata->osc_in_cmos_neg_inp_en = 1;
    -        ad9528_param.pdata->pll1_feedback_div = 4;
    -        ad9528_param.pdata->pll1_feedback_src_vcxo = 0; /* VCO */
    +                //user conf.
    +                ad9528_param.pdata->osc_in_diff_en = 1;
    +        ad9528_param.pdata->pll1_feedback_div = 1;//4;
    +        ad9528_param.pdata->pll1_feedback_src_vcxo = 0;/* VCO */
             ad9528_param.pdata->pll1_charge_pump_current_nA = 5000;
    -        ad9528_param.pdata->pll1_bypass_en = 0;
    +        ad9528_param.pdata->pll1_bypass_en = 1;//0;
             ad9528_param.pdata->pll2_vco_div_m1 = 3;
             ad9528_param.pdata->pll2_n2_div = 10;
             ad9528_param.pdata->pll2_r1_div = 1;

    Please send me the whole project folder that contains your modifications so that we get the same output, maybe something was missing.

    Regarding the TES generated profiles, please be aware that currently the ad9528 clocking settings are not used by no-OS. no-OS hardcodes ad9528 settings for this project and this might be the source of troubles for you. Only the talise_config.c/.h are used by no-OS driver from the profile.

Reply
  • Hi ,

    I've tried your profile and code on hardware based on 2019_R2 branch, however I got a different result:

    Hello
    rx_clkgen: MMCM-PLL locked (121333000 Hz)
    tx_clkgen: MMCM-PLL locked (121333000 Hz)
    rx_os_clkgen: MMCM-PLL locked (121333000 Hz)
    rx_adxcvr: OK (4853320 kHz)
    tx_adxcvr: OK (4853320 kHz)
    rx_os_adxcvr: OK (4853320 kHz)
    talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.521121266925568005
    ERROR: 247: TALISE_waitArmCmdStatus() failed due to thrown ARM error. ARM time out 
    error: TALISE_waitInitCals() failed
    Bye
    

    What I did was to use the profile from the archive and replace the app_clocking.c file from the archive (with some adaptations, I think you put a file from master, not from 2019_R2 in the archive):

    diff --git a/projects/adrv9009/src/app/app_clocking.c b/projects/adrv9009/src/app/app_clocking.c
    index 7a86dc213..4bf741d39 100644
    --- a/projects/adrv9009/src/app/app_clocking.c
    +++ b/projects/adrv9009/src/app/app_clocking.c
    @@ -124,7 +124,6 @@ adiHalErr_t clocking_init(uint32_t rx_div40_rate_hz,
                     .pll1_ref_prio_ctrl = 0xE5,
                     .sync_pin_mode = 0x1,
                     .high_performance_mode_clock_dist_en = true,
    -                .high_performance_mode_pll_vco_en = true,
                     .pulse_gen_mode = 0x0,
             };
     
    @@ -286,36 +285,49 @@ adiHalErr_t clocking_init(uint32_t rx_div40_rate_hz,
             ad9528_channels[13].driver_mode = DRIVER_MODE_LVDS;
             ad9528_channels[13].divider_phase = 0;
             ad9528_channels[13].signal_source = SOURCE_VCO;
    +        //user conf.
    +        ad9528_channels[13].channel_divider = 5;
     
             // fpga device clock
             ad9528_channels[1].output_dis = 0;
             ad9528_channels[1].driver_mode = DRIVER_MODE_LVDS;
             ad9528_channels[1].divider_phase = 0;
             ad9528_channels[1].signal_source = SOURCE_VCO;
    +        //user conf.
    +        ad9528_channels[1].channel_divider = 5;
     
             // adrv9009 sysref
             ad9528_channels[12].output_dis = 0;
             ad9528_channels[12].driver_mode = DRIVER_MODE_LVDS;
             ad9528_channels[12].divider_phase = 0;
             ad9528_channels[12].signal_source = SOURCE_SYSREF_VCO;
    +        //user conf.
    +        ad9528_channels[12].channel_divider = 5;
     
             // fpga sysref
             ad9528_channels[3].output_dis = 0;
             ad9528_channels[3].driver_mode = DRIVER_MODE_LVDS;
             ad9528_channels[3].divider_phase = 0;
             ad9528_channels[3].signal_source = SOURCE_SYSREF_VCO;
    +        //user conf.
    +        ad9528_channels[3].channel_divider = 5;
    +
    +        // user
    +        //ad9528_param.pdata->ref_mode = REF_MODE_REVERT_TO_REFA;
     
             // ad9528 settings
             ad9528_param.pdata->spi3wire = 0;
    -        ad9528_param.pdata->vcxo_freq = 122880000;
    +        ad9528_param.pdata->vcxo_freq = 121333000;
             ad9528_param.pdata->refa_en = 1;
             ad9528_param.pdata->refa_diff_rcv_en = 1;
             ad9528_param.pdata->refa_r_div = 1;
             ad9528_param.pdata->osc_in_cmos_neg_inp_en = 1;
    -        ad9528_param.pdata->pll1_feedback_div = 4;
    -        ad9528_param.pdata->pll1_feedback_src_vcxo = 0; /* VCO */
    +                //user conf.
    +                ad9528_param.pdata->osc_in_diff_en = 1;
    +        ad9528_param.pdata->pll1_feedback_div = 1;//4;
    +        ad9528_param.pdata->pll1_feedback_src_vcxo = 0;/* VCO */
             ad9528_param.pdata->pll1_charge_pump_current_nA = 5000;
    -        ad9528_param.pdata->pll1_bypass_en = 0;
    +        ad9528_param.pdata->pll1_bypass_en = 1;//0;
             ad9528_param.pdata->pll2_vco_div_m1 = 3;
             ad9528_param.pdata->pll2_n2_div = 10;
             ad9528_param.pdata->pll2_r1_div = 1;

    Please send me the whole project folder that contains your modifications so that we get the same output, maybe something was missing.

    Regarding the TES generated profiles, please be aware that currently the ad9528 clocking settings are not used by no-OS. no-OS hardcodes ad9528 settings for this project and this might be the source of troubles for you. Only the talise_config.c/.h are used by no-OS driver from the profile.

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