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ADRV9009 rx_jesd Measured Link Clock

Hi, 

I am working with ADRV9009-W/PCBZ at ZCU102 board. When i look at the initial report through UART, i discover measured link clock and reported link clock different form each other. Is it normal? 

rx_clkgen: MMCM-PLL locked (122880000 Hz)
tx_clkgen: MMCM-PLL locked (61440000 Hz)
rx_os_clkgen: MMCM-PLL locked (61440000 Hz)
rx_adxcvr: OK (4915200 kHz)
tx_adxcvr: OK (2457600 kHz)
rx_os_adxcvr: OK (2457600 kHz)
talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.263882790666240005
talise: Calibrations completed successfully
rx_jesd status:
        Link is enabled
        Measured Link Clock: 98.308 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 3.840 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
tx_jesd status:
        Link is enabled
        Measured Link Clock: 49.155 MHz
        Reported Link Clock: 61.440 MHz
        Lane rate: 2457.600 MHz
        Lane rate / 40: 61.440 MHz
        LMFC rate: 3.840 MHz
        SYNC~: deasserted
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd status:
        Link is enabled
        Measured Link Clock: 49.153 MHz
        Reported Link Clock: 61.440 MHz
        Lane rate: 2457.600 MHz
        Lane rate / 40: 61.440 MHz
        LMFC rate: 3.840 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
tx_dac: Successfully initialized (98309326 Hz)
rx_adc: Successfully initialized (98307800 Hz)



fix
[edited by: ee-bhan at 9:55 AM (GMT -4) on 18 May 2022]
  • Hi,

    No, this is not expected - measured and reported should match. Did you change anything in our default reference design?

    Thanks,
    Dragos

  • Hi  ,

    I removed the S_AXI_HP2 (output of rx_dma) only because i am filtering the data before using it. Other than that everything same. 

  • Hi to me,

    Analog employees are respond very late so it is so hard to take some help in here. For people whom interesting with this problem, I am going to explain the reason behind this problem.

    In the Analog Device's reference design, ADI IPs use 100 MHz clk (pl_clk0) and JESD IPs calculate the "Measured Link Clock" with a counter that counts with this 100 MHz clock. 

    I was changed that JESD IP's working clock rate to 125 MHz for some reasons (doesn't matter why). So counter count faster than it had to. Consequently "Measured Link Clock" is seems slower than it has. This is not a problem for ADRV9009. It works properly. 

    The rate between measured and reported links equal to rate between reference clock hertz and new clock hertz. You can take as a proof: 98.308/122.880 = 100/125