axi_dmac wrong register write

Greetings!

I'm using the ad7616 evaluation board. As I was having a problem with the axi dmac. I find the following problems:

  1. in dmac transfer function this line call axi_dmac_function  to write 0x1 at the register 0x408 (macro definition of register) is but instead of writing on the target register the it writes on the register 0x404 as shown in the below picture. I don't know why it's happening. 
  2.  After that when moving forward and it ignores this piece of loops code and directly goes to the return value.

Regards

  • Hello,

    This seems like a memory access violation. Can you try increasing the stack ad heap size of the program and see if it's any better?

    Also what carrier, no-OS, HDL code and vivado/vitis distribution are you using?

    Regards,
    Andrei

  • Hello Andrei,

    I increased the stack and heap size from 2000 to 10000 but the same is happening as I mentioned above.

    I'm using HDL 2019_r2 and n0-OS 2019_r2 branches, the Vivado and Vitis version is 2020.1, 

    Regards

  • Hello,

    What motherboard are you using with the eval board? If it's not one of the supported designs or a custom one, make sure that the libraries available support dynamic allocation. We are doing it quite a lot in the driver and there was recently a similar issue caused by the libraries not having malloc and calloc.

    Regards,
    Andrei

  • Hello  

    Thank you for your reply and support. I'm using an AX7015 board. malloc is working as there is no error while running the malloc command in the program. 

  • I think in this case malloc can fail without error. Can you check that the axi_dmac handler pointer is consistent throughout the stack trace down to the Xil_out call? That is, make sure it is allocated properly from the start and is not changed anywhere.

    Regards,
    Andrei

  • Hello

    Can you please give me a hint about how to trace down this? I really appreciate your response. 

    Regards

  • Hello,

    I looked at the code a little closer and it seems to me now that it's behaving as intended.

    1. So for the first issue: you are seeing that we write a value to 408 register, but apparently the 404 register is written instead. This is only an illusion. We shall look at the wiki describing the DMAC IP to see what is really happening. When writing 1 to the 408 register the IP should queue a transfer as soon as possible and then clear the bit back to 0. Since there are no transfers in progress and the IP is ready to go the bit is quickly cleared and the transfer is queued. Register 404 has the number of the next transfer to be queued. It starts at 0 and is pushed to 1 once the first transfer is queued. This all happens so fast that the debugger never catches the 408 as being 1.
    2. The second behavior is that the code ignores the code below the while loop you pointed out. That is because of the 'if' clause above. If we have a cyclic transfer we don't wait for it to queue and finish anymore because it happens continuously until we stop it. We will see here that the SPI engine offload driver sets the DMA transfer to be cyclic if we do not specify other flags. And no flags are specified here.

    Regards,
    Andrei

  • Hello

    Thank you so much for your detailed explanation. Now, I thought DMA is not working because of this issue but from your explanation, this issue is ruled out. So, the real problem is the adc_valid signal (which I mentioned in another thread) which is not going high, and the write enable signal remains low. Due to which data remains in the queue and is not being written on DDR memory.

    Regards