Hi,I am using the hdl release 'hdl_2019_r1'. And I am using the project in zc706 and EVAL-ADRV9008/9. And i am using no-os release '2019_R1'.
1. I want to know what frequency of the clk_0 in the picture below., is it 122.88MHz ? It's seems equal to the "lane rate / 40" and lane rate = 4915.2MHz.
2. what frequency is the clk in the picture below ? Is it 250MHz?
3. I notice that the clk_0 connect to the link_clk of rx_adrv9009_tp_core.
Is the link_clk as sample frequency of adc_data_0~3 ? If it isn't ,which clk is ? and the freq?
I am looking forward to ur reply.. Thanks for ur help..