what frequency of the link clk of the adc data of adrv9009 reference design?

Hello, 

all clocks you mention in your post should be lane rate / 40  (122.88 MHz in you case)

At the TPL one beat of link_clk can contain one or more samples per channel. That depends on the JESD parameters. In this case is 1 sample per beat,  so the link_clk matches the sample clock.

Laszlo

Hello, 

all clocks you mention in your post should be lane rate / 40  (122.88 MHz in you case)

At the TPL one beat of link_clk can contain one or more samples per channel. That depends on the JESD parameters. In this case is 1 sample per beat,  so the link_clk matches the sample clock.

Laszlo

Thank you,Laszlo.

can u confirm that the clk marked in the picture below is also lane rate / 40 (122.88 MHz in my case)?

The input of the clock gen is connected to an util_adxcr  out clock.  That depends on the ref clock the transceiver receives and the divider the software sets (Can be div with 2  or bypass  div with 1).

So this is more a no-os question. I will move the question to the no-os forum.

Laszlo