AD7770

Hello,

I don't think we have HDL for controlling AD7770, but we have a No-OS driver. 

Moving the question to No-OS forum for comments.

Regards,

Adrian

Hi Adrian ,

Thanks for the Support

My doubt is  which pin in AD7770 used to control DRDY generation. My assumption is  start signal in AD7770 should be low for 1 MCLK clock cycle for every DRDY generation.  Could you please confirm the same.  

Hello,

I apologize for the late reply.

I think yo are correct that you need to drive the Start pin to control the sampling of the chip. Alternatively, I think you can use the DISABLE CLOCKS TO ADC CHANNEL REGISTER (register 8) to disable all channels, if you don't want to use the Start bit. 

Lastly, I suggest posting the question in the Precision ADC forum because they might be able to provide you with a more complete response.

Regards,
Andrei