I already built successfully adrv9001/zc706 projects with guidance from https://wiki.analog.com/resources/fpga/docs/build on Vivado 2020.1.
Now, I want to build no-OS project for this hdl design to test adrv9001. I follow the link https://wiki.analog.com/resources/eval/user-guides/adrv9002/no-os-setup to do it but it's not successfully.
The problems are:
1. With Xilinx vitis 2020.1, can not generate system_top.hdl (like in the guide), with vitis only system_top.xsa file is generated
2. How to build this no-OS project, it's not clear in the link above (using Vitis or another compiler, step to step to make,..?)
Please help me if you know!